1: Mon Dec 22 12:37:06 1997  Ian Lance Taylor  <ian@cygnus.com>
    2: 
    3:         * mips-opc.c: Add FP_D to s.d instruction flags.
    4: 
    5: Wed Dec 17 11:38:29 1997  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
    6: 
    7:         * m68k-opc.c (halt, pulse): Enable them on the 68060.
    8: 
    9: Tue Dec 16 15:22:53 1997  Fred Fish  <fnf@cygnus.com>
   10: 
   11:         * tic80-opc.c (tic80_opcodes): Revert change that put the 32 bit
   12:         PC relative offset forms before the 15 bit forms.  An assembler command
   13:         line option now chooses the default.
   14: 
   15: Tue Dec 16 15:22:51 1997  Michael Meissner  <meissner@cygnus.com>
   16: 
   17:         * d30v-opc.c (d30v_opcode_table): Set new flags bits
   18:         FLAG_{2WORD,MUL{16,32},ADDSUBppp}, in appropriate instructions.
   19: 
   20: 1997-12-15  Brendan Kehoe  <brendan@lisa.cygnus.com>
   21: 
   22:         * configure: Only build libopcodes shared if --enable-shared's value
   23:         was `yes', or was set to `*opcodes*'.
   24:         * aclocal.m4: Likewise.
   25:         * NOTE: this really needs to be fixed in libtool/libtool.m4, the
   26:         original source of this bit of code.  It's not clear what the best fix
   27:         would be, though.
   28: 
   29: Fri Dec 12 11:57:04 1997  Fred Fish  <fnf@cygnus.com>
   30: 
   31:         * tic80-opc.c (OFF_SL_PC, OFF_SL_BR): Minor formatting change.
   32:         (tic80_opcodes): Reorder table entries to put the 32 bit PC relative
   33:         offset forms before the 15 bit forms, to default to the long forms.
   34: 
   35: Fri Dec 12 01:32:30 1997  Richard Henderson  <rth@cygnus.com>
   36: 
   37:         * alpha-opc.c (cvttq/*u*): Remove, as that suffix is invalid.
   38: 
   39: Wed Dec 10 17:42:35 1997  Nick Clifton  <nickc@cygnus.com>
   40: 
   41:         * arm-dis.c (print_insn_little_arm): Prevent examination of stored
   42:         symbol if none is present.
   43:         (print_insn_big_arm):  Prevent examination of stored symbol if
   44:         none is present.
   45: 
   46: Thu Oct 23 21:13:37 1997  Fred Fish  <fnf@cygnus.com>
   47: 
   48:         * d10v-opc.c (d10v_opcodes): Correct entry for RTE.
   49: 
   50: Mon Dec  8 11:21:07 1997  Nick Clifton  <nickc@cygnus.com>
   51: 
   52:         * disassemble.c: Remove disasm_symaddr() function.
   53: 
   54:         * arm-dis.c: Use info->symbol instead of info->flags to determine
   55:         if disassmbly should be in Thumb or Arm mode.
   56: 
   57: Tue Dec  2 09:54:27 1997  Nick Clifton  <nickc@cygnus.com>
   58: 
   59:         * arm-dis.c: Add support for disassembling Thumb opcodes.
   60:         (print_insn_thumb): New function.
   61: 
   62:         * disassemble.c (disasm_symaddr): New function.
   63: 
   64:         * arm-opc.h: Display nop pseudo ops alongside equivalent disassembly.
   65:         (thumb_opcodes): Table of Thumb opcodes.
   66: 
   67: Mon Dec  1 12:25:57 1997  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
   68: 
   69:         * m68k-opc.c (btst): Change Dd@s to Dd;b.
   70: 
   71:         * m68k-dis.c (print_insn_arg): Recognize 'm', 'n', 'o', 'p', 'q',
   72:         and 'v' as operand types.
   73: 
   74: Mon Dec  1 11:56:50 1997  Ian Lance Taylor  <ian@cygnus.com>
   75: 
   76:         * m68k-opc.c: Add argument for lpstop.  From Olivier Carmona
   77:         <olivier.carmona@di.epfl.ch>.
   78:         * m68k-dis.c (print_insn_m68k): Handle special case of lpstop,
   79:         which has a two word opcode with a one word argument.
   80: 
   81: Sun Nov 23 22:25:21 1997  Michael Meissner  <meissner@cygnus.com>
   82: 
   83:         * d30v-opc.c (d30v_opcode_table, case cmpu): Immediate field is
   84:         unsigned, not signed.
   85:         (d30v_format_table): Add SHORT_CMPU cases for cmpu.
   86: 
   87: Tue Nov 18 23:10:03 1997  J"orn Rennecke  <amylaar@cygnus.co.uk>
   88: 
   89:         * d10v-dis.c (print_operand):
   90:         Split OPERAND_FLAG into OPERAND_FFLAG and OPERAND_CFLAG.
   91: 
   92: Tue Nov 18 18:45:14 1997  J"orn Rennecke  <amylaar@cygnus.co.uk>
   93: 
   94:         * d10v-opc.c (OPERAND_FLAG): Split into:
   95:         (OPERAND_FFLAG, OPERAND_CFLAG) .
   96:         (FSRC): Split into:
   97:         (FFSRC, CFSRC).
   98: 
   99: Thu Nov 13 11:05:33 1997  Gavin Koch  <gavin@cygnus.com>
  100: 
  101:         * mips-opc.c: Move the INSN_MACRO ISA value to the membership
  102:         field for all INSN_MACRO's.
  103:         * mips16-opc.c: same
  104: 
  105: Wed Nov 12 10:16:57 1997  Gavin Koch  <gavin@cygnus.com>
  106: 
  107:         * mips-opc.c (sync,cache): These are 3900 insns.
  108: 
  109: Tue Nov 11 23:53:41 1997  J"orn Rennecke <amylaar@cygnus.co.uk>
  110: 
  111:         sh-opc.h (sh_table): Remove ftst/nan.
  112: 
  113: Tue Oct 28 17:59:32 1997  Ken Raeburn  <raeburn@cygnus.com>
  114: 
  115:         * mips-opc.c (ffc, ffs): Fix mask.
  116: 
  117: Tue Oct 28 16:34:54 1997  Michael Meissner  <meissner@cygnus.com>
  118: 
  119:         * d30v-opc.c (pre_defined_registers): Add eit_vb, int_s, and int_m
  120:         control registers.
  121: 
  122: Mon Oct 27 22:34:03 1997  Ken Raeburn  <raeburn@cygnus.com>
  123: 
  124:         * mips-opc.c: Fix bug in mask for "not" pseudo-instruction.
  125:         (WR_HILO, RD_HILO, MOD_HILO): New macros.
  126: 
  127: Mon Oct 27 22:34:03 1997  Ken Raeburn  <raeburn@cygnus.com>
  128: 
  129:         * mips-opc.c: Fix bug in mask for "not" pseudo-instruction.
  130:         (WR_HILO, RD_HILO, MOD_HILO): New macros.
  131: 
  132: Thu Oct 23 14:57:58 1997  Nick Clifton  <nickc@cygnus.com>
  133: 
  134:         * v850-dis.c (disassemble): Replace // with /* ... */
  135: 
  136: Wed Oct 22 17:33:21 1997  Richard Henderson  <rth@cygnus.com>
  137: 
  138:         * sparc-opc.c: Add wr & rd for v9a asr's.
  139:         * sparc-dis.c (print_insn_sparc): Recognize '_' and '/' for v9a asr's.
  140:         (v9a_asr_reg_names): New variable.
  141:         Patch from David Miller <davem@vger.rutgers.edu>.
  142: 
  143: Wed Oct 22 17:18:02 1997  Richard Henderson  <rth@cygnus.com>
  144: 
  145:         * sparc-opc.c (v9notv9a): New insn type.
  146:         (IMPDEP): Move to the end to not conflict with edge8 et al.
  147:         Patch from David Miller <davem@vger.rutgers.edu>.
  148: 
  149: Fri Oct 17 13:18:53 1997  Gavin Koch  <gavin@cygnus.com>
  150: 
  151:         * mips-opc.c (bnezl,beqzl): Mark these as also tx39.
  152: 
  153: Thu Oct 16 11:55:20 1997  Gavin Koch  <gavin@cygnus.com>
  154: 
  155:         * mips-opc.c: Note that 'jalx' is (probably incorrectly) marked I1.
  156: 
  157: Tue Oct 14 16:10:31 1997  Nick Clifton  <nickc@cygnus.com>
  158: 
  159:         * v850-dis.c (disassemble): Use new symbol_at_address_func() field
  160:         of disassemble_info structure to determine if an overlay address
  161:         has a matching symbol in low memory.
  162: 
  163:         * dis-buf.c (generic_symbol_at_address): New (dummy) function for
  164:         new symbol_at_address_func field in disassemble_info structure.
  165: 
  166: Fri Oct 10 16:44:52 1997  Nick Clifton  <nickc@cygnus.com>
  167: 
  168:         * v850-opc.c (extract_d22): Use signed arithmatic.
  169: 
  170: Tue Oct  7 23:40:43 1997  Gavin Koch  <gavin@cygnus.com>
  171: 
  172:         * mips-opc.c: Three op mult is not an ISA insn.
  173: 
  174: Tue Oct  7 23:37:21 1997  Gavin Koch  <gavin@cygnus.com>
  175: 
  176:         * mips-opc.c: Fix formatting.
  177: 
  178: Fri Oct  3 17:26:54 1997  Ian Lance Taylor  <ian@cygnus.com>
  179: 
  180:         * i386-dis.c (OP_E): Explicitly sign extend 8 bit values, rather
  181:         than assuming that char is signed.  Explicitly sign extend 16 bit
  182:         values, rather than assuming that short is 16 bits.
  183:         (OP_sI, OP_J, OP_DIR): Likewise.
  184: 
  185: Thu Oct  2 13:36:45 1997  Nick Clifton  <nickc@cygnus.com>
  186: 
  187:         * v850-dis.c (v850_sreg_names): Use symbolic names for higher
  188:         system registers.
  189: 
  190: Wed Oct  1 16:58:54 1997  Nick Clifton  <nickc@cygnus.com>
  191: 
  192:         * v850-opc.c: Fix typo in comment.
  193: 
  194:         * v850-dis.c (disassemble): Add test of processor type when
  195:         determining opcodes.
  196: 
  197: Wed Oct  1 14:10:20 1997  Ian Lance Taylor  <ian@cygnus.com>
  198: 
  199:         * configure.in: Use a diversion to set enable_shared before the
  200:         arguments are parsed.
  201:         * configure: Rebuild.
  202: 
  203: Thu Sep 25 13:04:59 1997  Ian Lance Taylor  <ian@cygnus.com>
  204: 
  205:         * m68k-opc.c (TBL1): Use ! rather than `.
  206:         * m68k-dis.c (print_insn_arg): Remove ` operand specifier.
  207: 
  208: Wed Sep 24 11:29:35 1997  Ian Lance Taylor  <ian@cygnus.com>
  209: 
  210:         * m68k-opc.c: Correct bchg, bclr, bset, and btst on ColdFire.
  211: 
  212:         * m68k-opc.c: Accept tst{b,w,l} with immediate operands on cpu32.
  213: 
  214:         * m68k-opc.c: Correct movew of an immediate operand to %sr or %ccr
  215:         for mcf5200.
  216: 
  217:         * configure.in: Call AC_CHECK_TOOL before AM_PROG_LIBTOOL.
  218:         * aclocal.m4: Rebuild with new libtool.
  219:         * configure: Rebuild.
  220: 
  221: Fri Sep 19 11:45:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
  222: 
  223:         * v850-opc.c ("cmov"): Order reg param r1, r2 not r2, r2.
  224: 
  225: Thu Sep 18 11:21:43 1997  Doug Evans  <dje@canuck.cygnus.com>
  226: 
  227:         * sparc-opc.c (sparclet_cpreg_table): Add %ccsr2, %cccrr, %ccrstr.
  228: 
  229: Tue Sep 16 15:18:20 1997  Nick Clifton  <nickc@cygnus.com>
  230: 
  231:         * v850-opc.c (v850_opcodes): Further rearrangements.
  232: 
  233: Tue Sep 16 16:12:11 1997  Ken Raeburn  <raeburn@cygnus.com>
  234: 
  235:         * d30v-opc.c (rot2h, sra2h, srl2h insns): Revert last change.
  236: 
  237: Tue Sep 16 09:48:50 1997  Nick Clifton  <nickc@cygnus.com>
  238: 
  239:         * v850-opc.c (v850_opcodes): Fields reordered to allow assembler
  240:         parser to work.
  241: 
  242: Tue Sep 16 10:01:00 1997  Gavin Koch  <gavin@cygnus.com>
  243: 
  244:         * mips-opc.c: Added tx39 insns sdbbp, rfe, and deret.
  245: 
  246: Mon Sep 15 18:31:52 1997  Nick Clifton  <nickc@cygnus.com>
  247: 
  248:         * v850-opc.c: Initialise processors field of v850_opcode structure.
  249: 
  250: Wed Aug 27 21:42:39 1997  Ken Raeburn  <raeburn@cygnus.com>
  251: 
  252:         Merge changes from Martin Hunt:
  253: 
  254:         * d30v-opc.c: Change mvfacc to accept 6-bit unsigned values.
  255: 
  256:         * d30v-opc.c (pre_defined_registers): Add control registers from 0-63.
  257:         (d30v_opcode_tabel): Add dbt, rtd, srah, and srlh instructions. Fix
  258:         rot2h, sra2h, and srl2h to use new SHORT_A5S format.
  259: 
  260:         * d30v-dis.c (print_insn): Fix disassembly of SHORT_D2 opcodes.
  261: 
  262:         * d30v-dis.c (print_insn): First operand of d*i (delayed
  263:         branch) instructions is relative.
  264: 
  265:         * d30v-opc.c (d30v_opcode_table): Change form for repeati.
  266:         (d30v_operand_table): Add IMM6S3 type.
  267:         (d30v_format_table): Change SHORT_D2. Add LONG_Db.
  268: 
  269:         * d30v-dis.c: Fix bug with ".s" and ".l" extensions
  270:         and cmp instructions.
  271: 
  272:         * d30v-opc.c: Correct entries for repeat*, and sat*.
  273:         Make IMM5 unsigned. Create IMM6U and IMM12S3U operand
  274:         types. Correct several formats.
  275: 
  276:         * d30v-opc.c: (pre_defined_registers): Add dpsw and dpc.
  277: 
  278:         * d30v-opc.c (pre_defined_registers): Change control registers.
  279: 
  280:         * d30v-opc.c (d30v_format_table): Correct SHORT_C1 and
  281:         SHORT_C2.  Manual was incorrect.
  282: 
  283:         * d30v-dis.c (lookup_opcode):  Return value now indicates
  284:         if an opcode has a short and a long form.  Used for deciding
  285:         to append a ".s" or ".l".
  286:         (print_insn): Append a ".s" to an instruction if it is
  287:         the short form and ".l" if it is a long form. Do not append
  288:         anything if the instruction has only one possible size.
  289: 
  290:         * d30v-opc.c: Change mulx2h to require an even register.
  291:         New form: SHORT_A2; a SHORT_A form that needs an even
  292:         register as the first operand.
  293: 
  294:         * d30v-dis.c (print_insn_d30v): Fix problem where the last
  295:         instruction was not being disassembled if there were an odd
  296:         number of instructions.
  297: 
  298:         * d30v-opc.c (SHORT_M2, LONG_M2):  Two new forms.
  299: 
  300: Fri Sep 12 11:43:54 1997  Nick Clifton  <nickc@cygnus.com>
  301: 
  302:         * v850-dis.c (disassemble): Improved display of register lists.
  303: 
  304: Thu Sep 11 17:35:10 1997  Doug Evans  <dje@canuck.cygnus.com>
  305: 
  306:         * sparc-opc.c (sparc_opcodes): Fix assembler args to
  307:         fzeros, fones, fsrc1, fsrc1s, fsrc2s, fnot1, fnot1s, fnot2s,
  308:         fors, fnors, fands, fnands, fxors, fxnors, fornot1s, fornot2s,
  309:         fandnot1s, fandnot2s.
  310: 
  311: Tue Sep  9 10:03:49 1997  Doug Evans  <dje@canuck.cygnus.com>
  312: 
  313:         * sparc-opc.c (sparc_opcodes): Fix op3 field for fcmpq/fcmpeq.
  314: 
  315: Mon Sep  8 14:06:59 1997  Doug Evans  <dje@canuck.cygnus.com>
  316: 
  317:         * cgen-asm.c (cgen_parse_address): New argument resultp.
  318:         All callers updated.
  319:         * m32r-asm.c (parse_h_hi16): Right shift numbers by 16.
  320: 
  321: Tue Sep  2 18:39:08 1997  Jeffrey A Law  (law@cygnus.com)
  322: 
  323:         * mn10200-dis.c (disassemble): PC relative instructions are
  324:         relative to the next instruction, not the current instruction.
  325: 
  326: Tue Sep  2 15:41:55 1997  Nick Clifton  <nickc@cygnus.com>
  327: 
  328:         * v850-dis.c (disassemble): Only signed extend values that are not
  329:         returned by extract functions.
  330:         Remove use of V850_OPERAND_ADJUST_SHORT_MEMORY flag.
  331: 
  332: Tue Sep  2 15:39:40 1997  Nick Clifton  <nickc@cygnus.com>
  333: 
  334:         * v850-opc.c: Update comments.  Remove use of
  335:         V850_OPERAND_ADJUST_SHORT_MEMORY.  Fix several operand patterns.
  336: 
  337: Tue Aug 26 09:42:28 1997  Nick Clifton  <nickc@cygnus.com>
  338: 
  339:         * v850-opc.c (MOVHI): Immediate parameter is unsigned.
  340: 
  341: Mon Aug 25 15:58:07 1997  Christopher Provenzano  <proven@cygnus.com>
  342: 
  343:         * configure: Rebuilt with latest devo autoconf for NT support.
  344: 
  345: Fri Aug 22 10:35:15 1997  Nick Clifton  <nickc@cygnus.com>
  346: 
  347:         * v850-dis.c (disassemble): Use curly brace syntax for register
  348:         lists.
  349: 
  350:         * v850-opc.c (v850_opcodes[]): Add NOT_R0 flag to decect cases
  351:         where r0 is being used as a destination register.
  352: 
  353: Thu Aug 21 11:09:09 1997  Nick Clifton  <nickc@cygnus.com>
  354: 
  355:         * v850-opc.c (v850_opcodes[]): Move divh opcodes next to each other.
  356: 
  357: Tue Aug 19 10:59:59 1997  Richard Henderson  <rth@cygnus.com>
  358: 
  359:         * alpha-opc.c (alpha_opcodes): Fix hw_rei_stall mungage.
  360: 
  361: Mon Aug 18 11:10:03 1997  Nick Clifton  <nickc@cygnus.com>
  362: 
  363:         * v850-opc.c (v850_opcodes[]): Remove use of flag field.
  364:         * v850-opc.c (v850_opcodes[]): Add support for reversed short load
  365:         opcodes..
  366: 
  367: Mon Aug 18 11:08:25 1997  Nick Clifton  <nickc@cygnus.com>
  368: 
  369:         * configure (cgen_files): Add support for v850e target.
  370:         * configure.in (cgen_files):  Add support for v850e target.
  371: 
  372: Mon Aug 18 11:08:25 1997  Nick Clifton  <nickc@cygnus.com>
  373: 
  374:         * configure (cgen_files): Add support for v850ea target.
  375:         * configure.in (cgen_files):  Add support for v850ea target.
  376: 
  377: Fri Aug 15 05:17:48 1997  Doug Evans  <dje@canuck.cygnus.com>
  378: 
  379:         * configure.in (bfd_arc_arch): Add.
  380:         * configure: Rebuild.
  381:         * Makefile.am (ALL_MACHINES): Add arc-dis.lo, arc-opc.lo.
  382:         * Makefile.in: Rebuild.
  383:         * arc-dis.c, arc-opc.c: New files.
  384:         * disassemble.c (ARCH_all): Define ARCH_arc.
  385:         (disassembler): Add ARC support.
  386: 
  387: Wed Aug 13 18:52:11 1997  Nick Clifton  <nickc@cygnus.com>
  388: 
  389:         * v850-dis.c (disassemble): Add support for v850EA instructions.
  390: 
  391:         * v850-opc.c (insert_i5div, extract_i5div): New Functions.
  392:         (v850_opcodes): Add v850EA instructions.
  393: 
  394:         * v850-dis.c (disassemble): Add support for v850E instructions.
  395: 
  396:         * v850-opc.c (insert_d5_4, extract_d5_4, insert_d16_16,
  397:         extract_d16_16, insert_i9, extract_i9, insert_u9, extract_u9,
  398:         insert_spe, extract_spe): New Functions.
  399:         (v850_opcodes): Add v850E instructions.
  400: 
  401:         * v850-opc.c: Reorganised and re-layed out to improve readability
  402:         and portability.
  403: 
  404: Tue Aug  5 23:09:31 1997  Ian Lance Taylor  <ian@cygnus.com>
  405: 
  406:         * configure: Rebuild with autoconf 2.12.1.
  407: 
  408: Mon Aug  4 12:02:16 1997  Ian Lance Taylor  <ian@cygnus.com>
  409: 
  410:         * aclocal.m4, configure: Rebuild with new automake patches.
  411: 
  412: Fri Aug  1 13:02:04 1997  Ian Lance Taylor  <ian@cygnus.com>
  413: 
  414:         * configure.in: Set enable_shared before AM_PROG_LIBTOOL.
  415:         * acinclude.m4: Just include acinclude.m4 from BFD.
  416:         * aclocal.m4, configure: Rebuild.
  417: 
  418: Thu Jul 31 21:44:42 1997  Ian Lance Taylor  <ian@cygnus.com>
  419: 
  420:         * Makefile.am: New file, based on old Makefile.in.
  421:         * acconfig.h: New file.
  422:         * acinclude.m4: New file.
  423:         * stamp-h.in: New file.
  424:         * configure.in: Call AM_INIT_AUTOMAKE and AM_PROG_LIBTOOL.
  425:         Removed shared library handling; now handled by libtool.  Replace
  426:         AC_CONFIG_HEADER with AM_CONFIG_HEADER.  Call AM_MAINTAINER_MODE,
  427:         AM_CYGWIN32, and AM_EXEEXT.  Replace AC_PROG_INSTALL with
  428:         AM_PROG_INSTALL.  Change all .o files to .lo.  Remove stamp-h
  429:         handling in AC_OUTPUT.
  430:         * dep-in.sed: Change .o to .lo.
  431:         * Makefile.in: Now built with automake.
  432:         * aclocal.m4: Now built with aclocal.
  433:         * config.in, configure: Rebuild.
  434: 
  435: Mon Jul 28 21:52:24 1997  Jeffrey A Law  (law@cygnus.com)
  436: 
  437:         * mips-opc.c: Fix typo/thinko in "eret" instruction.
  438: 
  439: Thu Jul 24 13:03:26 1997  Doug Evans  <dje@canuck.cygnus.com>
  440: 
  441:         * sparc-opc.c (sparc_opcodes): Fix spelling on fpaddX, fpsubX insns.
  442:         Make array const.
  443:         * sparc-dis.c (sorted_opcodes): New static local.
  444:         (struct opcode_hash): `opcode' is pointer to const element.
  445:         (build_hash): First arg is now table of sorted pointers.
  446:         (print_insn_sparc): Sort opcodes by sorting table of pointers.
  447:         (compare_opcodes): Update.
  448: 
  449: Tue Jul 15 12:05:23 1997  Doug Evans  <dje@canuck.cygnus.com>
  450: 
  451:         * cgen-opc.c: #include <ctype.h>.
  452:         (hash_keyword_name): New arg `case_sensitive_p'.  Callers updated.
  453:         Handle case insensitive hashing.
  454:         (hash_keyword_value): Change type of `value' to unsigned int.
  455: 
  456: Thu Jul 10 12:56:10 1997  Jeffrey A Law  (law@cygnus.com)
  457: 
  458:         * mips-opc.c (mips_builtin_opcodes): If an insn uses single
  459:         precision FP, mark it as such.  Likewise for double precision
  460:         FP.  Mark ISA1 insns.  Consolidate duplicate opcodes where
  461:         possible.
  462: 
  463: Wed Jun 25 15:25:57 1997  Felix Lee  <flee@cirdan.cygnus.com>
  464: 
  465:         * ppc-opc.c (extract_nsi): make unsigned expression signed before
  466:         negating it.
  467:         (UNUSED): remove one level of parens, so MSVC doesn't choke on
  468:         nesting depth when all the macros are expanded.
  469: 
  470: Tue Jun 17 17:02:17 1997  Ian Lance Taylor  <ian@cygnus.com>
  471: 
  472:         * sparc-opc.c: The fcmp v9a instructions take an integer register
  473:         as a destination, not a floating point register.  From Christian
  474:         Kuehnke <Christian.Kuehnke@arbi.Informatik.Uni-Oldenburg.DE>.
  475: 
  476: Mon Jun 16 14:13:18 1997  Ian Lance Taylor  <ian@cygnus.com>
  477: 
  478:         * m68k-dis.c (print_insn_arg): Print case 7.2 using %pc@()
  479:         syntax.  From Roman Hodek
  480:         <rnhodek@faui22c.informatik.uni-erlangen.de>.
  481: 
  482:         * i386-dis.c (twobyte_has_modrm): Fix pand.
  483: 
  484: Mon Jun 16 14:08:38 1997  Michael Taylor  <mbt@mit.edu>
  485: 
  486:         * i386-dis.c (dis386_twobyte): Fix pand and pandn.
  487: 
  488: Tue Jun 10 11:26:47 1997  H.J. Lu  <hjl@gnu.ai.mit.edu>
  489: 
  490:         * arm-dis.c: Add prototypes for arm_decode_shift and
  491:         print_insn_arm.
  492: 
  493: Mon Jun  2 11:39:04 1997  Gavin Koch  <gavin@cygnus.com>
  494: 
  495:         * mips-opc.c: Add r3900 insns.
  496: 
  497: Tue May 27 15:55:44 1997  Ian Lance Taylor  <ian@cygnus.com>
  498: 
  499:         * sh-dis.c (print_insn_shx): Change relmask to bfd_vma.  Don't
  500:         print delay slot instructions on the same line.  When using a PC
  501:         relative load, add a comment with the value being loaded if it can
  502:         be obtained.
  503: 
  504: Tue May 27 11:02:08 1997  Alan Modra  <alan@spri.levels.unisa.edu.au>
  505: 
  506:         * i386-dis.c (dis386[], dis386_twobyte[]): change pushl/popl
  507:         to pushS/popS for segment regs and byte constant so that
  508:         pushw/popw printed when in 16 bit data mode.
  509: 
  510:         * i386-dis.c (dis386[]): change cwtl, cltd to cWtS, cStd to
  511:         print cbtw, cwtd in 16 bit data mode.
  512:         * i386-dis.c (putop): extra case W to support above.
  513: 
  514:         * i386-dis.c (print_insn_x86): print addr32 prefix when given
  515:         address size prefix in 16 bit address mode.
  516: 
  517: Fri May 23 16:47:23 1997  Ian Lance Taylor  <ian@cygnus.com>
  518: 
  519:         * sh-dis.c: Reindent.  Rename local variable fprintf to
  520:         fprintf_fn.
  521: 
  522: Thu May 22 14:06:02 1997  Doug Evans  <dje@canuck.cygnus.com>
  523: 
  524:         * m32r-opc.c (m32r_cgen_insn_table, cmpui): Undo patch of May 2.
  525: 
  526: Tue May 20 11:26:27 1997  Gavin Koch  <gavin@cygnus.com>
  527: 
  528:         * mips-opc.c (mips_builtin_opcodes): Moved INSN_ISA field into new
  529:           field membership.
  530:         * mips16-opc.c (mip16_opcodes): same.
  531: 
  532: Mon May 12 15:10:53 1997  Jim Wilson  <wilson@cygnus.com>
  533: 
  534:         * m68k-opc.c (moveb): Change $d to %d.
  535: 
  536: Mon May  5 14:28:41 1997  Ian Lance Taylor  <ian@cygnus.com>
  537: 
  538:         * i386-dis.c: (dis386_twobyte): Add MMX instructions.
  539:         (twobyte_has_modrm): Likewise.
  540:         (grps): Likewise.
  541:         (OP_MMX, OP_EM, OP_MS): New static functions.
  542: 
  543:         * i386-dis.c: Revert patch of April 4.  The output now matches
  544:         what gcc generates.
  545: 
  546: Fri May  2 12:48:37 1997  Doug Evans  <dje@canuck.cygnus.com>
  547: 
  548:         * m32r-opc.c (m32r_cgen_insn_table, cmpui): Use $uimm16 instead
  549:         of $simm16.
  550: 
  551: Thu May  1 15:34:15 1997  Doug Evans  <dje@canuck.cygnus.com>
  552: 
  553:         * m32r-opc.h (CGEN_ARCH): Renamed from CGEN_CPU.
  554: 
  555: Tue Apr 15 12:40:08 1997  Ian Lance Taylor  <ian@cygnus.com>
  556: 
  557:         * Makefile.in (install): Depend upon installdirs.
  558:         (installdirs): New target.
  559: 
  560: Mon Apr 14 12:13:51 1997  Ian Lance Taylor  <ian@cygnus.com>
  561: 
  562:         From Thomas Graichen <graichen@rzpd.de>:
  563:         * configure.in: Use ${CONFIG_SHELL} when running $ac_config_sub.
  564:         * configure: Rebuild.
  565: 
  566: Sun Apr 13 17:50:41 1997  Doug Evans  <dje@canuck.cygnus.com>
  567: 
  568:         * cgen-*.c, m32r-*.c: #include sysdep.h instead of config.h.
  569:         Delete string{,s}.h support.
  570: 
  571: Thu Apr 10 14:44:56 1997  Doug Evans  <dje@canuck.cygnus.com>
  572: 
  573:         * cgen-asm.c (cgen_parse_operand_fn): New global.
  574:         (cgen_parse_{{,un}signed_integer,address}): Update call to
  575:         cgen_parse_operand_fn.
  576:         (cgen_init_parse_operand): New function.
  577:         * m32r-asm.c (parse_insn_normal): cgen_init_parse_operand renamed
  578:         from cgen_asm_init_parse.
  579:         (m32r_cgen_assemble_insn): New operand `errmsg'.
  580:         Delete call to as_bad, return error message to caller.
  581:         (m32r_cgen_asm_hash_keywords): #if 0 out.
  582: 
  583: Wed Apr  9 12:05:25 1997  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
  584: 
  585:         * m68k-dis.c (print_insn_arg) [case 'd']: Print as address register,
  586:         not data register.
  587:         [case 'J']: Fix typo in register name.
  588: 
  589: Mon Apr  7 16:48:22 1997  Ian Lance Taylor  <ian@cygnus.com>
  590: 
  591:         * configure.in: Substitute SHLIB_LIBS.
  592:         * configure: Rebuild.
  593:         * Makefile.in (SHLIB_LIBS): New variable.
  594:         ($(SHLIB)): Use $(SHLIB_LIBS).
  595: 
  596: Mon Apr  7 11:45:44 1997  Doug Evans  <dje@canuck.cygnus.com>
  597: 
  598:         * cgen-dis.c (build_dis_hash_table): Fix xmalloc size computation.
  599: 
  600:         * cgen-opc.c (hash_keyword_name): Improve algorithm.
  601: 
  602:         * disassemble.c (disassembler): Handle m32r.
  603: 
  604: Fri Apr  4 12:29:38 1997  Doug Evans  <dje@canuck.cygnus.com>
  605: 
  606:         * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: New files.
  607:         * cgen-asm.c, cgen-dis.c, cgen-opc.c: New files.
  608:         * Makefile.in (CFILES): Add them.
  609:         (ALL_MACHINES): Add them.
  610:         (dependencies): Regenerate.
  611:         * configure.in (cgen_files): New variable.
  612:         (bfd_m32r_arch): Add entry.
  613:         * configure: Regenerate.
  614: 
  615: Fri Apr  4 14:04:16 1997  Ian Lance Taylor  <ian@cygnus.com>
  616: 
  617:         * configure.in: Correct file names for bfd_mn10[23]00_arch.
  618:         * configure: Rebuild.
  619: 
  620:         * Makefile.in: Rebuild dependencies.
  621: 
  622:         * d10v-dis.c: Include "ansidecl.h" before "opcode/d10v.h".
  623: 
  624:         * i386-dis.c (float_reg): Swap fsubrp and fsubp.  Swap fdivrp and
  625:         fdivp.
  626: 
  627: Thu Apr  3 13:22:45 1997  Ian Lance Taylor  <ian@cygnus.com>
  628: 
  629:         * Branched binutils 2.8.
  630: 
  631: Wed Apr  2 12:23:53 1997  Ian Lance Taylor  <ian@cygnus.com>
  632: 
  633:         * m10200-dis.c: Rename from mn10200-dis.c.
  634:         * m10200-opc.c: Rename from mn10200-opc.c.
  635:         * m10300-dis.c: Rename from mn10300-dis.c
  636:         * m10300-opc.c: Rename from mn10300-opc.c.
  637:         * Makefile.in: Update accordingly.
  638: 
  639:         * mips16-opc.c: Add mul and dmul macros.
  640: 
  641: Tue Apr  1 16:27:45 1997  Klaus Kaempf  <kkaempf@progis.de>
  642: 
  643:         * makefile.vms: Update CFLAGS, add clean target.
  644: 
  645: Fri Mar 28 12:10:09 1997  Ian Lance Taylor  <ian@cygnus.com>
  646: 
  647:         * mips-opc.c: Add "wait".  From Ralf Baechle
  648:         <ralf@gnu.ai.mit.edu>.
  649: 
  650:         * configure.in: Add stdlib.h to AC_CHECK_HEADERS list.
  651:         * configure, config.in: Rebuild.
  652:         * sysdep.h: Include <stdlib.h> if it exists.
  653:         * sparc-dis.c: Include <stdio.h> and "sysdep.h".  Don't include
  654:         <string.h>.
  655:         * Makefile.in: Rebuild dependencies.
  656: 
  657: Thu Mar 27 14:24:43 1997  Ian Lance Taylor  <ian@cygnus.com>
  658: 
  659:         * ppc-opc.c: Add PPC 403 instructions and extended opcodes.  From
  660:         Andrew Bray <andy@madhouse.demon.co.uk>.
  661: 
  662:         * mips-opc.c: Add cast when setting mips_opcodes.
  663: 
  664: Tue Mar 25 23:04:00 1997  Stu Grossman  (grossman@critters.cygnus.com)
  665: 
  666:         * v850-dis.c (disassemble):  Fix sign extension problem.
  667:         * v850-opc.c (extract_d*):  Fix sign extension problems to make
  668:         disassembly calculate branch offsets correctly.
  669: 
  670: Mon Mar 24 13:22:13 1997  Ian Lance Taylor  <ian@cygnus.com>
  671: 
  672:         * sh-opc.h: Add bf/s and bt/s as synonyms for bf.s and bt.s.
  673: 
  674:         * mips-opc.c: Add dctr and dctw.
  675: 
  676: Sun Mar 23 18:08:10 1997  Martin M. Hunt  <hunt@pizza.cygnus.com>
  677: 
  678:         * d30v-dis.c (print_insn): Change the way signed constants
  679:         are displayed.
  680: 
  681: Fri Mar 21 14:37:52 1997  Ian Lance Taylor  <ian@cygnus.com>
  682: 
  683:         * Makefile.in (BFD_H): New variable.
  684:         (HFILES): New variable.
  685:         (CFILES): Add all C files.
  686:         (.dep, .dep1, dep.sed, dep, dep-in): New targets.
  687:         Delete old dependencies, and build new ones.
  688:         * dep-in.sed: New file.
  689: 
  690: Thu Mar 20 19:03:30 1997  Philippe De Muyter  <phdm@info.ucl.ac.be>
  691: 
  692:         * m68k-opc.c (m68k_opcode_aliases): Added blo and blo{s,b,w,l}.
  693: 
  694: Tue Mar 18 14:17:03 1997  Jeffrey A Law  (law@cygnus.com)
  695: 
  696:         * mn10200-opc.c: Change "trap" to "syscall".
  697:         * mn10300-opc.c: Add new "syscall" instruction.
  698: 
  699: Mon Mar 17 08:48:03 1997  J.T. Conklin  <jtc@beauty.cygnus.com>
  700: 
  701:         * m68k-opc.c (m68k_opcodes): Provide correct entries for mulsl and
  702:         mulul insns on the coldfire.
  703: 
  704: Sat Mar 15 17:13:05 1997  Ian Lance Taylor  <ian@cygnus.com>
  705: 
  706:         * arm-dis.c (print_insn_arm): Don't print instruction bytes.
  707:         (print_insn_big_arm): Set bytes_per_chunk and display_endian.
  708:         (print_insn_little_arm): Likewise.
  709: 
  710: Fri Mar 14 15:08:59 1997  Ian Lance Taylor  <ian@cygnus.com>
  711: 
  712:         Based on patches from H.J. Lu <hjl@lucon.org>:
  713:         * i386-dis.c (fetch_data): Add prototype.
  714:         * m68k-dis.c (fetch_data): Add prototype.
  715:         (dummy_print_address): Add prototype.  Make static.
  716:         * ppc-opc.c (valid_bo): Add prototype.
  717:         * sparc-dis.c (build_hash_table): Add prototype.
  718:         (is_delayed_branch, compute_arch_mask): Add prototypes.
  719:         (print_insn_sparc): Make several local variables const.
  720:         (compare_opcodes): Change arguments to const PTR.  Add prototype.
  721:         * sparc-opc.c (arg): Change name field to be const.
  722:         (lookup_name, lookup_value): Add prototypes.  Change table and
  723:         name parameters to be const.
  724:         (sparc_encode_asi): Change name parameter to be const.
  725:         (sparc_encode_membar, sparc_encode_prefetch): Likewise.