1: /* CPU data for fr30.
    2: 
    3: THIS FILE IS MACHINE GENERATED WITH CGEN.
    4: 
    5: Copyright 1996-2007 Free Software Foundation, Inc.
    6: 
    7: This file is part of the GNU Binutils and/or GDB, the GNU debugger.
    8: 
    9:    This file is free software; you can redistribute it and/or modify
   10:    it under the terms of the GNU General Public License as published by
   11:    the Free Software Foundation; either version 3, or (at your option)
   12:    any later version.
   13: 
   14:    It is distributed in the hope that it will be useful, but WITHOUT
   15:    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   16:    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   17:    License for more details.
   18: 
   19:    You should have received a copy of the GNU General Public License along
   20:    with this program; if not, write to the Free Software Foundation, Inc.,
   21:    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
   22: 
   23: */
   24: 
   25: #include "sysdep.h"
   26: #include <stdio.h>
   27: #include <stdarg.h>
   28: #include "ansidecl.h"
   29: #include "bfd.h"
   30: #include "symcat.h"
   31: #include "fr30-desc.h"
   32: #include "fr30-opc.h"
   33: #include "opintl.h"
   34: #include "libiberty.h"
   35: #include "xregex.h"
   36: 
   37: /* Attributes.  */
   38: 
   39: static const CGEN_ATTR_ENTRY bool_attr[] =
   40: {
   41:   { "#f", 0 },
   42:   { "#t", 1 },
   43:   { 0, 0 }
   44: };
   45: 
   46: static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
   47: {
   48:   { "base", MACH_BASE },
   49:   { "fr30", MACH_FR30 },
   50:   { "max", MACH_MAX },
   51:   { 0, 0 }
   52: };
   53: 
   54: static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
   55: {
   56:   { "fr30", ISA_FR30 },
   57:   { "max", ISA_MAX },
   58:   { 0, 0 }
   59: };
   60: 
   61: const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] =
   62: {
   63:   { "MACH", & MACH_attr[0], & MACH_attr[0] },
   64:   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
   65:   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
   66:   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
   67:   { "RESERVED", &bool_attr[0], &bool_attr[0] },
   68:   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
   69:   { "SIGNED", &bool_attr[0], &bool_attr[0] },
   70:   { 0, 0, 0 }
   71: };
   72: 
   73: const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
   74: {
   75:   { "MACH", & MACH_attr[0], & MACH_attr[0] },
   76:   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
   77:   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
   78:   { "PC", &bool_attr[0], &bool_attr[0] },
   79:   { "PROFILE", &bool_attr[0], &bool_attr[0] },
   80:   { 0, 0, 0 }
   81: };
   82: 
   83: const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
   84: {
   85:   { "MACH", & MACH_attr[0], & MACH_attr[0] },
   86:   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
   87:   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
   88:   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
   89:   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
   90:   { "SIGNED", &bool_attr[0], &bool_attr[0] },
   91:   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
   92:   { "RELAX", &bool_attr[0], &bool_attr[0] },
   93:   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
   94:   { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
   95:   { 0, 0, 0 }
   96: };
   97: 
   98: const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
   99: {
  100:   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  101:   { "ALIAS", &bool_attr[0], &bool_attr[0] },
  102:   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  103:   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
  104:   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
  105:   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
  106:   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
  107:   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
  108:   { "RELAXED", &bool_attr[0], &bool_attr[0] },
  109:   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
  110:   { "PBB", &bool_attr[0], &bool_attr[0] },
  111:   { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
  112:   { 0, 0, 0 }
  113: };
  114: 
  115: /* Instruction set variants.  */
  116: 
  117: static const CGEN_ISA fr30_cgen_isa_table[] = {
  118:   { "fr30", 16, 16, 16, 48 },
  119:   { 0, 0, 0, 0, 0 }
  120: };
  121: 
  122: /* Machine variants.  */
  123: 
  124: static const CGEN_MACH fr30_cgen_mach_table[] = {
  125:   { "fr30", "fr30", MACH_FR30, 0 },
  126:   { 0, 0, 0, 0 }
  127: };
  128: 
  129: static CGEN_KEYWORD_ENTRY fr30_cgen_opval_gr_names_entries[] =
  130: {
  131:   { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
  132:   { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
  133:   { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
  134:   { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
  135:   { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
  136:   { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
  137:   { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
  138:   { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
  139:   { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
  140:   { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
  141:   { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
  142:   { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
  143:   { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
  144:   { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
  145:   { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
  146:   { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
  147:   { "ac", 13, {0, {{{0, 0}}}}, 0, 0 },
  148:   { "fp", 14, {0, {{{0, 0}}}}, 0, 0 },
  149:   { "sp", 15, {0, {{{0, 0}}}}, 0, 0 }
  150: };
  151: 
  152: CGEN_KEYWORD fr30_cgen_opval_gr_names =
  153: {
  154:   & fr30_cgen_opval_gr_names_entries[0],
  155:   19,
  156:   0, 0, 0, 0, ""
  157: };
  158: 
  159: static CGEN_KEYWORD_ENTRY fr30_cgen_opval_cr_names_entries[] =
  160: {
  161:   { "cr0", 0, {0, {{{0, 0}}}}, 0, 0 },
  162:   { "cr1", 1, {0, {{{0, 0}}}}, 0, 0 },
  163:   { "cr2", 2, {0, {{{0, 0}}}}, 0, 0 },
  164:   { "cr3", 3, {0, {{{0, 0}}}}, 0, 0 },
  165:   { "cr4", 4, {0, {{{0, 0}}}}, 0, 0 },
  166:   { "cr5", 5, {0, {{{0, 0}}}}, 0, 0 },
  167:   { "cr6", 6, {0, {{{0, 0}}}}, 0, 0 },
  168:   { "cr7", 7, {0, {{{0, 0}}}}, 0, 0 },
  169:   { "cr8", 8, {0, {{{0, 0}}}}, 0, 0 },
  170:   { "cr9", 9, {0, {{{0, 0}}}}, 0, 0 },
  171:   { "cr10", 10, {0, {{{0, 0}}}}, 0, 0 },
  172:   { "cr11", 11, {0, {{{0, 0}}}}, 0, 0 },
  173:   { "cr12", 12, {0, {{{0, 0}}}}, 0, 0 },
  174:   { "cr13", 13, {0, {{{0, 0}}}}, 0, 0 },
  175:   { "cr14", 14, {0, {{{0, 0}}}}, 0, 0 },
  176:   { "cr15", 15, {0, {{{0, 0}}}}, 0, 0 }
  177: };
  178: 
  179: CGEN_KEYWORD fr30_cgen_opval_cr_names =
  180: {
  181:   & fr30_cgen_opval_cr_names_entries[0],
  182:   16,
  183:   0, 0, 0, 0, ""
  184: };
  185: 
  186: static CGEN_KEYWORD_ENTRY fr30_cgen_opval_dr_names_entries[] =
  187: {
  188:   { "tbr", 0, {0, {{{0, 0}}}}, 0, 0 },
  189:   { "rp", 1, {0, {{{0, 0}}}}, 0, 0 },
  190:   { "ssp", 2, {0, {{{0, 0}}}}, 0, 0 },
  191:   { "usp", 3, {0, {{{0, 0}}}}, 0, 0 },
  192:   { "mdh", 4, {0, {{{0, 0}}}}, 0, 0 },
  193:   { "mdl", 5, {0, {{{0, 0}}}}, 0, 0 }
  194: };
  195: 
  196: CGEN_KEYWORD fr30_cgen_opval_dr_names =
  197: {
  198:   & fr30_cgen_opval_dr_names_entries[0],
  199:   6,
  200:   0, 0, 0, 0, ""
  201: };
  202: 
  203: static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
  204: {
  205:   { "ps", 0, {0, {{{0, 0}}}}, 0, 0 }
  206: };
  207: 
  208: CGEN_KEYWORD fr30_cgen_opval_h_ps =
  209: {
  210:   & fr30_cgen_opval_h_ps_entries[0],
  211:   1,
  212:   0, 0, 0, 0, ""
  213: };
  214: 
  215: static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
  216: {
  217:   { "r13", 0, {0, {{{0, 0}}}}, 0, 0 }
  218: };
  219: 
  220: CGEN_KEYWORD fr30_cgen_opval_h_r13 =
  221: {
  222:   & fr30_cgen_opval_h_r13_entries[0],
  223:   1,
  224:   0, 0, 0, 0, ""
  225: };
  226: 
  227: static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
  228: {
  229:   { "r14", 0, {0, {{{0, 0}}}}, 0, 0 }
  230: };
  231: 
  232: CGEN_KEYWORD fr30_cgen_opval_h_r14 =
  233: {
  234:   & fr30_cgen_opval_h_r14_entries[0],
  235:   1,
  236:   0, 0, 0, 0, ""
  237: };
  238: 
  239: static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
  240: {
  241:   { "r15", 0, {0, {{{0, 0}}}}, 0, 0 }
  242: };
  243: 
  244: CGEN_KEYWORD fr30_cgen_opval_h_r15 =
  245: {
  246:   & fr30_cgen_opval_h_r15_entries[0],
  247:   1,
  248:   0, 0, 0, 0, ""
  249: };
  250: 
  251: 
  252: /* The hardware table.  */
  253: 
  254: #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
  255: #define A(a) (1 << CGEN_HW_##a)
  256: #else
  257: #define A(a) (1 << CGEN_HW_/**/a)
  258: #endif
  259: 
  260: const CGEN_HW_ENTRY fr30_cgen_hw_table[] =
  261: {
  262:   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  263:   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  264:   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  265:   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  266:   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  267:   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
  268:   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  269:   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  270:   { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_dr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  271:   { "h-ps", HW_H_PS, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  272:   { "h-r13", HW_H_R13, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  273:   { "h-r14", HW_H_R14, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  274:   { "h-r15", HW_H_R15, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  275:   { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  276:   { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  277:   { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  278:   { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  279:   { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  280:   { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  281:   { "h-tbit", HW_H_TBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  282:   { "h-d0bit", HW_H_D0BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  283:   { "h-d1bit", HW_H_D1BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  284:   { "h-ccr", HW_H_CCR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  285:   { "h-scr", HW_H_SCR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  286:   { "h-ilm", HW_H_ILM, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  287:   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
  288: };
  289: 
  290: #undef A
  291: 
  292: 
  293: /* The instruction field table.  */
  294: 
  295: #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
  296: #define A(a) (1 << CGEN_IFLD_##a)
  297: #else
  298: #define A(a) (1 << CGEN_IFLD_/**/a)
  299: #endif
  300: 
  301: const CGEN_IFLD fr30_cgen_ifld_table[] =
  302: {
  303:   { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  304:   { FR30_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  305:   { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  306:   { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  307:   { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  308:   { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  309:   { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  310:   { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  311:   { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  312:   { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  313:   { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  314:   { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  315:   { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  316:   { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  317:   { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  318:   { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  319:   { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  320:   { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  321:   { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  322:   { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  323:   { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  324:   { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  325:   { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  326:   { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  327:   { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  328:   { FR30_F_I20, "f-i20", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
  329:   { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
  330:   { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  331:   { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  332:   { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  333:   { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  334:   { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  335:   { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  336:   { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
  337:   { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  338:   { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  339:   { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  340:   { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
  341:   { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  342:   { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  343:   { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  344:   { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  345:   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
  346: };
  347: 
  348: #undef A
  349: 
  350: 
  351: 
  352: /* multi ifield declarations */
  353: 
  354: const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [];
  355: 
  356: 
  357: /* multi ifield definitions */
  358: 
  359: const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [] =
  360: {
  361:     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I20_4] } },
  362:     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I20_16] } },
  363:     { 0, { (const PTR) 0 } }
  364: };
  365: 
  366: /* The operand table.  */
  367: 
  368: #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
  369: #define A(a) (1 << CGEN_OPERAND_##a)
  370: #else
  371: #define A(a) (1 << CGEN_OPERAND_/**/a)
  372: #endif
  373: #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
  374: #define OPERAND(op) FR30_OPERAND_##op
  375: #else
  376: #define OPERAND(op) FR30_OPERAND_/**/op
  377: #endif
  378: 
  379: const CGEN_OPERAND fr30_cgen_operand_table[] =
  380: {
  381: /* pc: program counter */
  382:   { "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0,
  383:     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_NIL] } }, 
  384:     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
  385: /* Ri: destination register */
  386:   { "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4,
  387:     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RI] } }, 
  388:     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  389: /* Rj: source register */
  390:   { "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4,
  391:     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJ] } }, 
  392:     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  393: /* Ric: target register coproc insn */
  394:   { "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4,
  395:     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RIC] } }, 
  396:     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  397: /* Rjc: source register coproc insn */
  398:   { "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4,
  399:     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJC] } }, 
  400:     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  401: /* CRi: coprocessor register */
  402:   { "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4,
  403:     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRI] } }, 
  404:     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  405: /* CRj: coprocessor register */
  406:   { "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4,
  407:     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRJ] } }, 
  408:     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  409: /* Rs1: dedicated register */
  410:   { "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4,
  411:     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS1] } }, 
  412:     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  413: /* Rs2: dedicated register */
  414:   { "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4,
  415:     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS2] } }, 
  416:     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  417: /* R13: General Register 13 */
  418:   { "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0,
  419:     { 0, { (const PTR) 0 } }, 
  420:     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  421: /* R14: General Register 14 */
  422:   { "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0,
  423:     { 0, { (const PTR) 0 } }, 
  424:     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  425: /* R15: General Register 15 */
  426:   { "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0,
  427:     { 0, { (const PTR) 0 } }, 
  428:     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  429: /* ps: Program Status register */
  430:   { "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0,
  431:     { 0, { (const PTR) 0 } }, 
  432:     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  433: /* u4: 4  bit unsigned immediate */
  434:   { "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
  435:     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4] } }, 
  436:     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
  437: /* u4c: 4  bit unsigned immediate */
  438:   { "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
  439:     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4C] } }, 
  440:     { 0|