1: /* This file is automatically generated by ia64-gen.  Do not edit!  */
    2: /* Copyright 2007  Free Software Foundation, Inc.
    3: 
    4:    This file is part of the GNU opcodes library.
    5: 
    6:    This library is free software; you can redistribute it and/or modify
    7:    it under the terms of the GNU General Public License as published by
    8:    the Free Software Foundation; either version 3, or (at your option)
    9:    any later version.
   10: 
   11:    It is distributed in the hope that it will be useful, but WITHOUT
   12:    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   13:    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   14:    License for more details.
   15: 
   16:    You should have received a copy of the GNU General Public License
   17:    along with this program; see the file COPYING.  If not, write to the
   18:    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
   19:    02110-1301, USA.  */
   20: static const char * const ia64_strings[] = {
   21:   "", "0", "1", "a", "acq", "add", "addl", "addp4", "adds", "alloc", "and",
   22:   "andcm", "b", "bias", "br", "break", "brl", "brp", "bsw", "c", "call",
   23:   "cexit", "chk", "cloop", "clr", "clrrrb", "cmp", "cmp4", "cmp8xchg16",
   24:   "cmpxchg1", "cmpxchg2", "cmpxchg4", "cmpxchg8", "cond", "cover", "ctop",
   25:   "czx1", "czx2", "d", "dep", "dpnt", "dptk", "e", "epc", "eq", "excl",
   26:   "exit", "exp", "extr", "f", "fabs", "fadd", "famax", "famin", "fand",
   27:   "fandcm", "fault", "fc", "fchkf", "fclass", "fclrf", "fcmp", "fcvt",
   28:   "fetchadd4", "fetchadd8", "few", "fill", "flushrs", "fma", "fmax",
   29:   "fmerge", "fmin", "fmix", "fmpy", "fms", "fneg", "fnegabs", "fnma",
   30:   "fnmpy", "fnorm", "for", "fpabs", "fpack", "fpamax", "fpamin", "fpcmp",
   31:   "fpcvt", "fpma", "fpmax", "fpmerge", "fpmin", "fpmpy", "fpms", "fpneg",
   32:   "fpnegabs", "fpnma", "fpnmpy", "fprcpa", "fprsqrta", "frcpa", "frsqrta",
   33:   "fselect", "fsetc", "fsub", "fswap", "fsxt", "fwb", "fx", "fxor", "fxu",
   34:   "g", "ga", "ge", "getf", "geu", "gt", "gtu", "h", "hint", "hu", "i", "ia",
   35:   "imp", "invala", "itc", "itr", "l", "ld1", "ld16", "ld2", "ld4", "ld8",
   36:   "ldf", "ldf8", "ldfd", "ldfe", "ldfp8", "ldfpd", "ldfps", "ldfs", "le",
   37:   "leu", "lfetch", "loadrs", "loop", "lr", "lt", "ltu", "lu", "m", "many",
   38:   "mf", "mix1", "mix2", "mix4", "mov", "movl", "mux1", "mux2", "nc", "ne",
   39:   "neq", "nge", "ngt", "nl", "nle", "nlt", "nm", "nop", "nr", "ns", "nt1",
   40:   "nt2", "nta", "nz", "or", "orcm", "ord", "pack2", "pack4", "padd1",
   41:   "padd2", "padd4", "pavg1", "pavg2", "pavgsub1", "pavgsub2", "pcmp1",
   42:   "pcmp2", "pcmp4", "pmax1", "pmax2", "pmin1", "pmin2", "pmpy2", "pmpyshr2",
   43:   "popcnt", "pr", "probe", "psad1", "pshl2", "pshl4", "pshladd2", "pshr2",
   44:   "pshr4", "pshradd2", "psub1", "psub2", "psub4", "ptc", "ptr", "r", "raz",
   45:   "rel", "ret", "rfi", "rsm", "rum", "rw", "s", "s0", "s1", "s2", "s3",
   46:   "sa", "se", "setf", "shl", "shladd", "shladdp4", "shr", "shrp", "sig",
   47:   "spill", "spnt", "sptk", "srlz", "ssm", "sss", "st1", "st16", "st2",
   48:   "st4", "st8", "stf", "stf8", "stfd", "stfe", "stfs", "sub", "sum", "sxt1",
   49:   "sxt2", "sxt4", "sync", "tak", "tbit", "tf", "thash", "tnat", "tpa",
   50:   "trunc", "ttag", "u", "unc", "unord", "unpack1", "unpack2", "unpack4",
   51:   "uss", "uus", "uuu", "vmsw", "w", "wexit", "wtop", "x", "xchg1", "xchg2",
   52:   "xchg4", "xchg8", "xf", "xma", "xmpy", "xor", "xuf", "z", "zxt1", "zxt2",
   53:   "zxt4",
   54: };
   55: 
   56: static const struct ia64_dependency
   57: dependencies[] = {
   58:   { "ALAT", 0, 0, 0, -1, NULL, },
   59:   { "AR[BSP]", 26, 0, 2, 17, NULL, },
   60:   { "AR[BSPSTORE]", 26, 0, 2, 18, NULL, },
   61:   { "AR[CCV]", 26, 0, 2, 32, NULL, },
   62:   { "AR[CFLG]", 26, 0, 2, 27, NULL, },
   63:   { "AR[CSD]", 26, 0, 2, 25, NULL, },
   64:   { "AR[EC]", 26, 0, 2, 66, NULL, },
   65:   { "AR[EFLAG]", 26, 0, 2, 24, NULL, },
   66:   { "AR[FCR]", 26, 0, 2, 21, NULL, },
   67:   { "AR[FDR]", 26, 0, 2, 30, NULL, },
   68:   { "AR[FIR]", 26, 0, 2, 29, NULL, },
   69:   { "AR[FPSR].sf0.controls", 30, 0, 2, -1, NULL, },
   70:   { "AR[FPSR].sf1.controls", 30, 0, 2, -1, NULL, },
   71:   { "AR[FPSR].sf2.controls", 30, 0, 2, -1, NULL, },
   72:   { "AR[FPSR].sf3.controls", 30, 0, 2, -1, NULL, },
   73:   { "AR[FPSR].sf0.flags", 30, 0, 2, -1, NULL, },
   74:   { "AR[FPSR].sf1.flags", 30, 0, 2, -1, NULL, },
   75:   { "AR[FPSR].sf2.flags", 30, 0, 2, -1, NULL, },
   76:   { "AR[FPSR].sf3.flags", 30, 0, 2, -1, NULL, },
   77:   { "AR[FPSR].traps", 30, 0, 2, -1, NULL, },
   78:   { "AR[FPSR].rv", 30, 0, 2, -1, NULL, },
   79:   { "AR[FSR]", 26, 0, 2, 28, NULL, },
   80:   { "AR[ITC]", 26, 0, 2, 44, NULL, },
   81:   { "AR[K%], % in 0 - 7", 1, 0, 2, -1, NULL, },
   82:   { "AR[LC]", 26, 0, 2, 65, NULL, },
   83:   { "AR[PFS]", 26, 0, 2, 64, NULL, },
   84:   { "AR[PFS]", 26, 0, 2, 64, NULL, },
   85:   { "AR[PFS]", 26, 0, 0, 64, NULL, },
   86:   { "AR[RNAT]", 26, 0, 2, 19, NULL, },
   87:   { "AR[RSC]", 26, 0, 2, 16, NULL, },
   88:   { "AR[SSD]", 26, 0, 2, 26, NULL, },
   89:   { "AR[UNAT]{%}, % in 0 - 63", 2, 0, 2, -1, NULL, },
   90:   { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 0, 0, -1, NULL, },
   91:   { "AR%, % in 48-63, 112-127", 4, 0, 2, -1, NULL, },
   92:   { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, },
   93:   { "BR%, % in 0 - 7", 5, 0, 0, -1, NULL, },
   94:   { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, },
   95:   { "CFM", 6, 0, 2, -1, NULL, },
   96:   { "CFM", 6, 0, 2, -1, NULL, },
   97:   { "CFM", 6, 0, 2, -1, NULL, },
   98:   { "CFM", 6, 0, 2, -1, NULL, },
   99:   { "CFM", 6, 0, 0, -1, NULL, },
  100:   { "CPUID#", 7, 0, 5, -1, NULL, },
  101:   { "CR[CMCV]", 27, 0, 3, 74, NULL, },
  102:   { "CR[DCR]", 27, 0, 3, 0, NULL, },
  103:   { "CR[EOI]", 27, 0, 7, 67, "SC Section 5.8.3.4, \"End of External Interrupt Register (EOI ?CR67)\" on page 2:119", },
  104:   { "CR[GPTA]", 27, 0, 3, 9, NULL, },
  105:   { "CR[IFA]", 27, 0, 1, 20, NULL, },
  106:   { "CR[IFA]", 27, 0, 3, 20, NULL, },
  107:   { "CR[IFS]", 27, 0, 3, 23, NULL, },
  108:   { "CR[IFS]", 27, 0, 1, 23, NULL, },
  109:   { "CR[IFS]", 27, 0, 1, 23, NULL, },
  110:   { "CR[IHA]", 27, 0, 3, 25, NULL, },
  111:   { "CR[IIM]", 27, 0, 3, 24, NULL, },
  112:   { "CR[IIP]", 27, 0, 3, 19, NULL, },
  113:   { "CR[IIP]", 27, 0, 1, 19, NULL, },
  114:   { "CR[IIPA]", 27, 0, 3, 22, NULL, },
  115:   { "CR[IPSR]", 27, 0, 3, 16, NULL, },
  116:   { "CR[IPSR]", 27, 0, 1, 16, NULL, },
  117:   { "CR[IRR%], % in 0 - 3", 8, 0, 3, -1, NULL, },
  118:   { "CR[ISR]", 27, 0, 3, 17, NULL, },
  119:   { "CR[ITIR]", 27, 0, 3, 21, NULL, },
  120:   { "CR[ITIR]", 27, 0, 1, 21, NULL, },
  121:   { "CR[ITM]", 27, 0, 3, 1, NULL, },
  122:   { "CR[ITV]", 27, 0, 3, 72, NULL, },
  123:   { "CR[IVA]", 27, 0, 4, 2, NULL, },
  124:   { "CR[IVR]", 27, 0, 7, 65, "SC Section 5.8.3.2, \"External Interrupt Vector Register (IVR ?CR65)\" on page 2:118", },
  125:   { "CR[LID]", 27, 0, 7, 64, "SC Section 5.8.3.1, \"Local ID (LID ?CR64)\" on page 2:117", },
  126:   { "CR[LRR%], % in 0 - 1", 9, 0, 3, -1, NULL, },
  127:   { "CR[PMV]", 27, 0, 3, 73, NULL, },
  128:   { "CR[PTA]", 27, 0, 3, 8, NULL, },
  129:   { "CR[TPR]", 27, 0, 3, 66, NULL, },
  130:   { "CR[TPR]", 27, 0, 7, 66, "SC Section 5.8.3.3, \"Task Priority Register (TPR ?CR66)\" on page 2:119", },
  131:   { "CR[TPR]", 27, 0, 1, 66, NULL, },
  132:   { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 0, 0, -1, NULL, },
  133:   { "DBR#", 11, 0, 2, -1, NULL, },
  134:   { "DBR#", 11, 0, 3, -1, NULL, },
  135:   { "DTC", 0, 0, 3, -1, NULL, },
  136:   { "DTC", 0, 0, 2, -1, NULL, },
  137:   { "DTC", 0, 0, 0, -1, NULL, },
  138:   { "DTC", 0, 0, 2, -1, NULL, },
  139:   { "DTC_LIMIT*", 0, 0, 2, -1, NULL, },
  140:   { "DTR", 0, 0, 3, -1, NULL, },
  141:   { "DTR", 0, 0, 2, -1, NULL, },
  142:   { "DTR", 0, 0, 3, -1, NULL, },
  143:   { "DTR", 0, 0, 0, -1, NULL, },
  144:   { "DTR", 0, 0, 2, -1, NULL, },
  145:   { "FR%, % in 0 - 1", 12, 0, 0, -1, NULL, },
  146:   { "FR%, % in 2 - 127", 13, 0, 2, -1, NULL, },
  147:   { "FR%, % in 2 - 127", 13, 0, 0, -1, NULL, },
  148:   { "GR0", 14, 0, 0, -1, NULL, },
  149:   { "GR%, % in 1 - 127", 15, 0, 0, -1, NULL, },
  150:   { "GR%, % in 1 - 127", 15, 0, 2, -1, NULL, },
  151:   { "IBR#", 16, 0, 2, -1, NULL, },
  152:   { "InService*", 17, 0, 3, -1, NULL, },
  153:   { "InService*", 17, 0, 2, -1, NULL, },
  154:   { "InService*", 17, 0, 2, -1, NULL, },
  155:   { "IP", 0, 0, 0, -1, NULL, },
  156:   { "ITC", 0, 0, 4, -1, NULL, },
  157:   { "ITC", 0, 0, 2, -1, NULL, },
  158:   { "ITC", 0, 0, 0, -1, NULL, },
  159:   { "ITC", 0, 0, 4, -1, NULL, },
  160:   { "ITC", 0, 0, 2, -1, NULL, },
  161:   { "ITC_LIMIT*", 0, 0, 2, -1, NULL, },
  162:   { "ITR", 0, 0, 2, -1, NULL, },
  163:   { "ITR", 0, 0, 4, -1, NULL, },
  164:   { "ITR", 0, 0, 2, -1, NULL, },
  165:   { "ITR", 0, 0, 0, -1, NULL, },
  166:   { "ITR", 0, 0, 4, -1, NULL, },
  167:   { "memory", 0, 0, 0, -1, NULL, },
  168:   { "MSR#", 18, 0, 5, -1, NULL, },
  169:   { "PKR#", 19, 0, 3, -1, NULL, },
  170:   { "PKR#", 19, 0, 0, -1, NULL, },
  171:   { "PKR#", 19, 0, 2, -1, NULL, },
  172:   { "PKR#", 19, 0, 2, -1, NULL, },
  173:   { "PMC#", 20, 0, 2, -1, NULL, },
  174:   { "PMC#", 20, 0, 7, -1, "SC Section 7.2.1, \"Generic Performance Counter Registers\" for PMC[0].fr on page 2:150", },
  175:   { "PMD#", 21, 0, 2, -1, NULL, },
  176:   { "PR0", 0, 0, 0, -1, NULL, },
  177:   { "PR%, % in 1 - 15", 22, 0, 2, -1, NULL, },
  178:   { "PR%, % in 1 - 15", 22, 0, 2, -1, NULL, },
  179:   { "PR%, % in 1 - 15", 22, 0, 0, -1, NULL, },
  180:   { "PR%, % in 16 - 62", 23, 0, 2, -1, NULL, },
  181:   { "PR%, % in 16 - 62", 23, 0, 2, -1, NULL, },
  182:   { "PR%, % in 16 - 62", 23, 0, 0, -1, NULL, },
  183:   { "PR63", 24, 0, 2, -1, NULL, },
  184:   { "PR63", 24, 0, 2, -1, NULL, },
  185:   { "PR63", 24, 0, 0, -1, NULL, },
  186:   { "PSR.ac", 28, 0, 1, 3, NULL, },
  187:   { "PSR.ac", 28, 0, 3, 3, NULL, },
  188:   { "PSR.ac", 28, 0, 2, 3, NULL, },
  189:   { "PSR.ac", 28, 0, 2, 3, NULL, },
  190:   { "PSR.be", 28, 0, 1, 1, NULL, },
  191:   { "PSR.be", 28, 0, 3, 1, NULL, },
  192:   { "PSR.be", 28, 0, 2, 1, NULL, },
  193:   { "PSR.be", 28, 0, 2, 1, NULL, },
  194:   { "PSR.bn", 28, 0, 2, 44, NULL, },
  195:   { "PSR.cpl", 28, 0, 1, 32, NULL, },
  196:   { "PSR.cpl", 28, 0, 2, 32, NULL, },
  197:   { "PSR.da", 28, 0, 2, 38, NULL, },
  198:   { "PSR.db", 28, 0, 3, 24, NULL, },
  199:   { "PSR.db", 28, 0, 2, 24, NULL, },
  200:   { "PSR.db", 28, 0, 2, 24, NULL, },
  201:   { "PSR.dd", 28, 0, 2, 39, NULL, },
  202:   { "PSR.dfh", 28, 0, 3, 19, NULL, },
  203:   { "PSR.dfh", 28, 0, 2, 19, NULL, },
  204:   { "PSR.dfh", 28, 0, 2, 19, NULL, },
  205:   { "PSR.dfl", 28, 0, 3, 18, NULL, },
  206:   { "PSR.dfl", 28, 0, 2, 18, NULL, },
  207:   { "PSR.dfl", 28, 0, 2, 18, NULL, },
  208:   { "PSR.di", 28, 0, 3, 22, NULL, },
  209:   { "PSR.di", 28, 0, 2, 22, NULL, },
  210:   { "PSR.di", 28, 0, 2, 22, NULL, },
  211:   { "PSR.dt", 28, 0, 3, 17, NULL, },
  212:   { "PSR.dt", 28, 0, 2, 17, NULL, },
  213:   { "PSR.dt", 28, 0, 2, 17, NULL, },
  214:   { "PSR.ed", 28, 0, 2, 43, NULL, },
  215:   { "PSR.i", 28, 0, 2, 14, NULL, },
  216:   { "PSR.ia", 28, 0, 0, 14, NULL, },
  217:   { "PSR.ic", 28, 0, 2, 13, NULL, },
  218:   { "PSR.ic", 28, 0, 3, 13, NULL, },
  219:   { "PSR.ic", 28, 0, 2, 13, NULL, },
  220:   { "PSR.id", 28, 0, 0, 14, NULL, },
  221:   { "PSR.is", 28, 0, 0, 14, NULL, },
  222:   { "PSR.it", 28, 0, 2, 14, NULL, },
  223:   { "PSR.lp", 28, 0, 2, 25, NULL, },
  224:   { "PSR.lp", 28, 0, 3, 25, NULL, },
  225:   { "PSR.lp", 28, 0, 2, 25, NULL, },
  226:   { "PSR.mc", 28, 0, 2, 35, NULL, },
  227:   { "PSR.mfh", 28, 0, 2, 5, NULL, },
  228:   { "PSR.mfl", 28, 0, 2, 4, NULL, },
  229:   { "PSR.pk", 28, 0, 3, 15, NULL, },
  230:   { "PSR.pk", 28, 0, 2, 15, NULL, },
  231:   { "PSR.pk", 28, 0, 2, 15, NULL, },
  232:   { "PSR.pp", 28, 0, 2, 21, NULL, },
  233:   { "PSR.ri", 28, 0, 0, 41, NULL, },
  234:   { "PSR.rt", 28, 0, 2, 27, NULL, },
  235:   { "PSR.rt", 28, 0, 3, 27, NULL, },
  236:   { "PSR.rt", 28, 0, 2, 27, NULL, },
  237:   { "PSR.si", 28, 0, 2, 23, NULL, },
  238:   { "PSR.si", 28, 0, 3, 23, NULL, },
  239:   { "PSR.si", 28, 0, 2, 23, NULL, },
  240:   { "PSR.sp", 28, 0, 2, 20, NULL, },
  241:   { "PSR.sp", 28, 0, 3, 20, NULL, },
  242:   { "PSR.sp", 28, 0, 2, 20, NULL, },
  243:   { "PSR.ss", 28, 0, 2, 40, NULL, },
  244:   { "PSR.tb", 28, 0, 3, 26, NULL, },
  245:   { "PSR.tb", 28, 0, 2, 26, NULL, },
  246:   { "PSR.tb", 28, 0, 2, 26, NULL, },
  247:   { "PSR.up", 28, 0, 2, 2, NULL, },
  248:   { "PSR.vm", 28, 0, 1, 46, NULL, },
  249:   { "PSR.vm", 28, 0, 2, 46, NULL, },
  250:   { "RR#", 25, 0, 3, -1, NULL, },
  251:   { "RR#", 25, 0, 2, -1, NULL, },
  252:   { "RSE", 29, 0, 2, -1, NULL, },
  253:   { "ALAT", 0, 1, 0, -1, NULL, },
  254:   { "AR[BSP]", 26, 1, 2, 17, NULL, },
  255:   { "AR[BSPSTORE]", 26, 1, 2, 18, NULL, },
  256:   { "AR[CCV]", 26, 1, 2, 32, NULL, },
  257:   { "AR[CFLG]", 26, 1, 2, 27, NULL, },
  258:   { "AR[CSD]", 26, 1, 2, 25, NULL, },
  259:   { "AR[EC]", 26, 1, 2, 66, NULL, },
  260:   { "AR[EFLAG]", 26, 1, 2, 24, NULL, },
  261:   { "AR[FCR]", 26, 1, 2, 21, NULL, },
  262:   { "AR[FDR]", 26, 1, 2, 30, NULL, },
  263:   { "AR[FIR]", 26, 1, 2, 29, NULL, },
  264:   { "AR[FPSR].sf0.controls", 30, 1, 2, -1, NULL, },
  265:   { "AR[FPSR].sf1.controls", 30, 1, 2, -1, NULL, },
  266:   { "AR[FPSR].sf2.controls", 30, 1, 2, -1, NULL, },
  267:   { "AR[FPSR].sf3.controls", 30, 1, 2, -1, NULL, },
  268:   { "AR[FPSR].sf0.flags", 30, 1, 0, -1, NULL, },
  269:   { "AR[FPSR].sf0.flags", 30, 1, 2, -1, NULL, },
  270:   { "AR[FPSR].sf0.flags", 30, 1, 2, -1, NULL, },
  271:   { "AR[FPSR].sf1.flags", 30, 1, 0, -1, NULL, },
  272:   { "AR[FPSR].sf1.flags", 30, 1, 2, -1, NULL, },
  273:   { "AR[FPSR].sf1.flags", 30, 1, 2, -1, NULL, },
  274:   { "AR[FPSR].sf2.flags", 30, 1, 0, -1, NULL, },
  275:   { "AR[FPSR].sf2.flags", 30, 1, 2, -1, NULL, },
  276:   { "AR[FPSR].sf2.flags", 30, 1, 2, -1, NULL, },
  277:   { "AR[FPSR].sf3.flags", 30, 1, 0, -1, NULL, },
  278:   { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, },
  279:   { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, },
  280:   { "AR[FPSR].rv", 30, 1, 2, -1, NULL, },
  281:   { "AR[FPSR].traps", 30, 1, 2, -1, NULL, },
  282:   { "AR[FSR]", 26, 1, 2, 28, NULL, },
  283:   { "AR[ITC]", 26, 1, 2, 44, NULL, },
  284:   { "AR[K%], % in 0 - 7", 1, 1, 2, -1, NULL, },
  285:   { "AR[LC]", 26, 1, 2, 65, NULL, },
  286:   { "AR[PFS]", 26, 1, 0, 64, NULL, },
  287:   { "AR[PFS]", 26, 1, 2, 64, NULL, },
  288:   { "AR[PFS]", 26, 1, 2, 64, NULL, },
  289:   { "AR[RNAT]", 26, 1, 2, 19, NULL, },
  290:   { "AR[RSC]", 26, 1, 2, 16, NULL, },
  291:   { "AR[SSD]", 26, 1, 2, 26, NULL, },
  292:   { "AR[UNAT]{%}, % in 0 - 63", 2, 1, 2, -1, NULL, },
  293:   { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 1, 0, -1, NULL, },
  294:   { "AR%, % in 48 - 63, 112-127", 4, 1, 2, -1, NULL, },
  295:   { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, },
  296:   { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, },
  297:   { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, },
  298:   { "BR%, % in 0 - 7", 5, 1, 0, -1, NULL, },
  299:   { "CFM", 6, 1, 2, -1, NULL, },
  300:   { "CPUID#", 7, 1, 0, -1, NULL, },
  301:   { "CR[CMCV]", 27, 1, 2, 74, NULL, },
  302:   { "CR[DCR]", 27, 1, 2, 0, NULL, },
  303:   { "CR[EOI]", 27, 1, 7, 67, "SC Section 5.8.3.4, \"End of External Interrupt Register (EOI ?CR67)\" on page 2:119", },
  304:   { "CR[GPTA]", 27, 1, 2, 9, NULL, },
  305:   { "CR[IFA]", 27, 1, 2, 20, NULL, },
  306:   { "CR[IFS]", 27, 1, 2, 23, NULL, },
  307:   { "CR[IHA]", 27, 1, 2, 25, NULL, },
  308:   { "CR[IIM]", 27, 1, 2, 24, NULL, },
  309:   { "CR[IIP]", 27, 1, 2, 19, NULL, },
  310:   { "CR[IIPA]", 27, 1, 2, 22, NULL, },
  311:   { "CR[IPSR]", 27, 1, 2, 16, NULL, },
  312:   { "CR[IRR%], % in 0 - 3", 8, 1, 2, -1, NULL, },
  313:   { "CR[ISR]", 27, 1, 2, 17, NULL, },
  314:   { "CR[ITIR]", 27, 1, 2, 21, NULL, },
  315:   { "CR[ITM]", 27, 1, 2, 1, NULL, },
  316:   { "CR[ITV]", 27, 1, 2, 72, NULL, },
  317:   { "CR[IVA]", 27, 1, 2, 2, NULL, },
  318:   { "CR[IVR]", 27, 1, 7, 65, "SC", },
  319:   { "CR[LID]", 27, 1, 7, 64, "SC", },
  320:   { "CR[LRR%], % in 0 - 1", 9, 1, 2, -1, NULL, },
  321:   { "CR[PMV]", 27, 1, 2, 73, NULL, },
  322:   { "CR[PTA]", 27, 1, 2, 8, NULL, },
  323:   { "CR[TPR]", 27, 1, 2, 66, NULL, },
  324:   { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 1, 0, -1, NULL, },
  325:   { "DBR#", 11, 1, 2, -1, NULL, },
  326:   { "DTC", 0, 1, 0, -1, NULL, },
  327:   { "DTC", 0, 1, 2, -1, NULL, },
  328:   { "DTC", 0, 1, 2, -1, NULL, },
  329:   { "DTC_LIMIT*", 0, 1, 2, -1, NULL, },
  330:   { "DTR", 0, 1, 2, -1, NULL, },
  331:   { "DTR", 0, 1, 2, -1, NULL, },
  332:   { "DTR", 0, 1, 2, -1, NULL, },
  333:   { "DTR", 0, 1, 0, -1, NULL, },
  334:   { "FR%, % in 0 - 1", 12, 1, 0, -1, NULL, },
  335:   { "FR%, % in 2 - 127", 13, 1, 2, -1, NULL, },
  336:   { "GR0", 14, 1, 0, -1, NULL, },
  337:   { "GR%, % in 1 - 127", 15, 1, 2, -1, NULL, },
  338:   { "IBR#", 16, 1, 2, -1, NULL, },
  339:   { "InService*", 17, 1, 7, -1, "SC", },
  340:   { "IP", 0, 1, 0, -1, NULL, },
  341:   { "ITC", 0, 1, 0, -1, NULL, },
  342:   { "ITC", 0, 1, 2, -1, NULL, },
  343:   { "ITC", 0, 1, 2, -1, NULL, },
  344:   { "ITR", 0, 1, 2, -1, NULL, },
  345:   { "ITR", 0, 1, 2, -1, NULL, },
  346:   { "ITR", 0, 1, 0, -1, NULL, },
  347:   { "memory", 0, 1, 0, -1, NULL, },
  348:   { "MSR#", 18, 1, 7, -1, "SC", },
  349:   { "PKR#", 19, 1, 0, -1, NULL, },
  350:   { "PKR#", 19, 1, 0, -1, NULL, },
  351:   { "PKR#", 19, 1, 2, -1, NULL, },
  352:   { "PMC#", 20, 1, 2, -1, NULL, },
  353:   { "PMD#", 21, 1, 2, -1, NULL, },
  354:   { "PR0", 0, 1, 0, -1, NULL, },
  355:   { "PR%, % in 1 - 15", 22, 1, 0, -1, NULL, },
  356:   { "PR%, % in 1 - 15", 22, 1, 0, -1, NULL, },
  357:   { "PR%, % in 1 - 15", 22, 1, 2, -1, NULL, },
  358:   { "PR%, % in 1 - 15", 22, 1, 2, -1, NULL, },
  359:   { "PR%, % in 16 - 62", 23, 1, 0, -1, NULL, },
  360:   { "PR%, % in 16 - 62", 23, 1, 0, -1, NULL, },
  361:   { "PR%, % in 16 - 62", 23, 1, 2, -1, NULL, },
  362:   { "PR%, % in 16 - 62", 23, 1, 2, -1, NULL, },
  363:   { "PR63", 24, 1, 0, -1, NULL, },
  364:   { "PR63", 24, 1, 0, -1, NULL, },
  365:   { "PR63", 24,