1: /* alpha-dis.c -- Disassemble Alpha AXP instructions
    2:    Copyright 1996, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
    3:    Contributed by Richard Henderson <rth@tamu.edu>,
    4:    patterned after the PPC opcode handling written by Ian Lance Taylor.
    5: 
    6: This file is part of GDB, GAS, and the GNU binutils.
    7: 
    8: GDB, GAS, and the GNU binutils are free software; you can redistribute
    9: them and/or modify them under the terms of the GNU General Public
   10: License as published by the Free Software Foundation; either version
   11: 2, or (at your option) any later version.
   12: 
   13: GDB, GAS, and the GNU binutils are distributed in the hope that they
   14: will be useful, but WITHOUT ANY WARRANTY; without even the implied
   15: warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
   16: the GNU General Public License for more details.
   17: 
   18: You should have received a copy of the GNU General Public License
   19: along with this file; see the file COPYING.  If not, write to the Free
   20: Software Foundation, 59 Temple Place - Suite 330, Boston, MA
   21: 02111-1307, USA.  */
   22: 
   23: #include <stdio.h>
   24: #include "dis-asm.h"
   25: 
   26: /* The opcode table is an array of struct alpha_opcode.  */
   27: 
   28: struct alpha_opcode
   29: {
   30:   /* The opcode name.  */
   31:   const char *name;
   32: 
   33:   /* The opcode itself.  Those bits which will be filled in with
   34:      operands are zeroes.  */
   35:   unsigned opcode;
   36: 
   37:   /* The opcode mask.  This is used by the disassembler.  This is a
   38:      mask containing ones indicating those bits which must match the
   39:      opcode field, and zeroes indicating those bits which need not
   40:      match (and are presumably filled in by operands).  */
   41:   unsigned mask;
   42: 
   43:   /* One bit flags for the opcode.  These are primarily used to
   44:      indicate specific processors and environments support the
   45:      instructions.  The defined values are listed below. */
   46:   unsigned flags;
   47: 
   48:   /* An array of operand codes.  Each code is an index into the
   49:      operand table.  They appear in the order which the operands must
   50:      appear in assembly code, and are terminated by a zero.  */
   51:   unsigned char operands[4];
   52: };
   53: 
   54: /* The table itself is sorted by major opcode number, and is otherwise
   55:    in the order in which the disassembler should consider
   56:    instructions.  */
   57: extern const struct alpha_opcode alpha_opcodes[];
   58: extern const unsigned alpha_num_opcodes;
   59: 
   60: /* Values defined for the flags field of a struct alpha_opcode.  */
   61: 
   62: /* CPU Availability */
   63: #define AXP_OPCODE_BASE  0x0001  /* Base architecture -- all cpus.  */
   64: #define AXP_OPCODE_EV4   0x0002  /* EV4 specific PALcode insns.  */
   65: #define AXP_OPCODE_EV5   0x0004  /* EV5 specific PALcode insns.  */
   66: #define AXP_OPCODE_EV6   0x0008  /* EV6 specific PALcode insns.  */
   67: #define AXP_OPCODE_BWX   0x0100  /* Byte/word extension (amask bit 0).  */
   68: #define AXP_OPCODE_CIX   0x0200  /* "Count" extension (amask bit 1).  */
   69: #define AXP_OPCODE_MAX   0x0400  /* Multimedia extension (amask bit 8).  */
   70: 
   71: #define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6))
   72: 
   73: /* A macro to extract the major opcode from an instruction.  */
   74: #define AXP_OP(i)       (((i) >> 26) & 0x3F)
   75: 
   76: /* The total number of major opcodes. */
   77: #define AXP_NOPS        0x40
   78: 
   79: ^L
   80: /* The operands table is an array of struct alpha_operand.  */
   81: 
   82: struct alpha_operand
   83: {
   84:   /* The number of bits in the operand.  */
   85:   unsigned int bits : 5;
   86: 
   87:   /* How far the operand is left shifted in the instruction.  */
   88:   unsigned int shift : 5;
   89: 
   90:   /* The default relocation type for this operand.  */
   91:   signed int default_reloc : 16;
   92: 
   93:   /* One bit syntax flags.  */
   94:   unsigned int flags : 16;
   95: 
   96:   /* Insertion function.  This is used by the assembler.  To insert an
   97:      operand value into an instruction, check this field.
   98: 
   99:      If it is NULL, execute
  100:          i |= (op & ((1 << o->bits) - 1)) << o->shift;
  101:      (i is the instruction which we are filling in, o is a pointer to
  102:      this structure, and op is the opcode value; this assumes twos
  103:      complement arithmetic).
  104: 
  105:      If this field is not NULL, then simply call it with the
  106:      instruction and the operand value.  It will return the new value
  107:      of the instruction.  If the ERRMSG argument is not NULL, then if
  108:      the operand value is illegal, *ERRMSG will be set to a warning
  109:      string (the operand will be inserted in any case).  If the
  110:      operand value is legal, *ERRMSG will be unchanged (most operands
  111:      can accept any value).  */
  112:   unsigned (*insert) PARAMS ((unsigned instruction, int op,
  113:                               const char **errmsg));
  114: 
  115:   /* Extraction function.  This is used by the disassembler.  To
  116:      extract this operand type from an instruction, check this field.
  117: 
  118:      If it is NULL, compute
  119:          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
  120:          if ((o->flags & AXP_OPERAND_SIGNED) != 0
  121:              && (op & (1 << (o->bits - 1))) != 0)
  122:            op -= 1 << o->bits;
  123:      (i is the instruction, o is a pointer to this structure, and op
  124:      is the result; this assumes twos complement arithmetic).
  125: 
  126:      If this field is not NULL, then simply call it with the
  127:      instruction value.  It will return the value of the operand.  If
  128:      the INVALID argument is not NULL, *INVALID will be set to
  129:      non-zero if this operand type can not actually be extracted from
  130:      this operand (i.e., the instruction does not match).  If the
  131:      operand is valid, *INVALID will not be changed.  */
  132:   int (*extract) PARAMS ((unsigned instruction, int *invalid));
  133: };
  134: 
  135: /* Elements in the table are retrieved by indexing with values from
  136:    the operands field of the alpha_opcodes table.  */
  137: 
  138: extern const struct alpha_operand alpha_operands[];
  139: extern const unsigned alpha_num_operands;
  140: 
  141: /* Values defined for the flags field of a struct alpha_operand.  */
  142: 
  143: /* Mask for selecting the type for typecheck purposes */
  144: #define AXP_OPERAND_TYPECHECK_MASK                                      \
  145:   (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR |            \
  146:    AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED |        \
  147:    AXP_OPERAND_UNSIGNED)
  148: 
  149: /* This operand does not actually exist in the assembler input.  This
  150:    is used to support extended mnemonics, for which two operands fields
  151:    are identical.  The assembler should call the insert function with
  152:    any op value.  The disassembler should call the extract function,
  153:    ignore the return value, and check the value placed in the invalid
  154:    argument.  */
  155: #define AXP_OPERAND_FAKE        01
  156: 
  157: /* The operand should be wrapped in parentheses rather than separated
  158:    from the previous by a comma.  This is used for the load and store
  159:    instructions which want their operands to look like "Ra,disp(Rb)".  */
  160: #define AXP_OPERAND_PARENS      02
  161: 
  162: /* Used in combination with PARENS, this supresses the supression of
  163:    the comma.  This is used for "jmp Ra,(Rb),hint".  */
  164: #define AXP_OPERAND_COMMA       04
  165: 
  166: /* This operand names an integer register.  */
  167: #define AXP_OPERAND_IR          010
  168: 
  169: /* This operand names a floating point register.  */
  170: #define AXP_OPERAND_FPR         020
  171: 
  172: /* This operand is a relative branch displacement.  The disassembler
  173:    prints these symbolically if possible.  */
  174: #define AXP_OPERAND_RELATIVE    040
  175: 
  176: /* This operand takes signed values.  */
  177: #define AXP_OPERAND_SIGNED      0100
  178: 
  179: /* This operand takes unsigned values.  This exists primarily so that
  180:    a flags value of 0 can be treated as end-of-arguments.  */
  181: #define AXP_OPERAND_UNSIGNED    0200
  182: 
  183: /* Supress overflow detection on this field.  This is used for hints. */
  184: #define AXP_OPERAND_NOOVERFLOW  0400
  185: 
  186: /* Mask for optional argument default value.  */
  187: #define AXP_OPERAND_OPTIONAL_MASK 07000
  188: 
  189: /* This operand defaults to zero.  This is used for jump hints.  */
  190: #define AXP_OPERAND_DEFAULT_ZERO 01000
  191: 
  192: /* This operand should default to the first (real) operand and is used
  193:    in conjunction with AXP_OPERAND_OPTIONAL.  This allows
  194:    "and $0,3,$0" to be written as "and $0,3", etc.  I don't like
  195:    it, but it's what DEC does.  */
  196: #define AXP_OPERAND_DEFAULT_FIRST 02000
  197: 
  198: /* Similarly, this operand should default to the second (real) operand.
  199:    This allows "negl $0" instead of "negl $0,$0".  */
  200: #define AXP_OPERAND_DEFAULT_SECOND 04000
  201: 
  202: ^L
  203: /* Register common names */
  204: 
  205: #define AXP_REG_V0      0
  206: #define AXP_REG_T0      1
  207: #define AXP_REG_T1      2
  208: #define AXP_REG_T2      3
  209: #define AXP_REG_T3      4
  210: #define AXP_REG_T4      5
  211: #define AXP_REG_T5      6
  212: #define AXP_REG_T6      7
  213: #define AXP_REG_T7      8
  214: #define AXP_REG_S0      9
  215: #define AXP_REG_S1      10
  216: #define AXP_REG_S2      11
  217: #define AXP_REG_S3      12
  218: #define AXP_REG_S4      13
  219: #define AXP_REG_S5      14
  220: #define AXP_REG_FP      15
  221: #define AXP_REG_A0      16
  222: #define AXP_REG_A1      17
  223: #define AXP_REG_A2      18
  224: #define AXP_REG_A3      19
  225: #define AXP_REG_A4      20
  226: #define AXP_REG_A5      21
  227: #define AXP_REG_T8      22
  228: #define AXP_REG_T9      23
  229: #define AXP_REG_T10     24
  230: #define AXP_REG_T11     25
  231: #define AXP_REG_RA      26
  232: #define AXP_REG_PV      27
  233: #define AXP_REG_T12     27
  234: #define AXP_REG_AT      28
  235: #define AXP_REG_GP      29
  236: #define AXP_REG_SP      30
  237: #define AXP_REG_ZERO    31
  238: 
  239: #define bfd_mach_alpha_ev4  0x10
  240: #define bfd_mach_alpha_ev5  0x20
  241: #define bfd_mach_alpha_ev6  0x30
  242: 
  243: enum bfd_reloc_code_real {
  244:     BFD_RELOC_23_PCREL_S2,
  245:     BFD_RELOC_ALPHA_HINT
  246: };
  247: 
  248: /* This file holds the Alpha AXP opcode table.  The opcode table includes
  249:    almost all of the extended instruction mnemonics.  This permits the
  250:    disassembler to use them, and simplifies the assembler logic, at the
  251:    cost of increasing the table size.  The table is strictly constant
  252:    data, so the compiler should be able to put it in the text segment.
  253: 
  254:    This file also holds the operand table.  All knowledge about inserting
  255:    and extracting operands from instructions is kept in this file.
  256: 
  257:    The information for the base instruction set was compiled from the
  258:    _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE,
  259:    version 2.
  260: 
  261:    The information for the post-ev5 architecture extensions BWX, CIX and
  262:    MAX came from version 3 of this same document, which is also available
  263:    on-line at http://ftp.digital.com/pub/Digital/info/semiconductor
  264:    /literature/alphahb2.pdf
  265: 
  266:    The information for the EV4 PALcode instructions was compiled from
  267:    _DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware
  268:    Reference Manual_, Digital Order Number EC-Q9ZUA-TE, preliminary
  269:    revision dated June 1994.
  270: 
  271:    The information for the EV5 PALcode instructions was compiled from
  272:    _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital
  273:    Order Number EC-QAEQB-TE, preliminary revision dated April 1995.  */
  274: ^L
  275: /* Local insertion and extraction functions */
  276: 
  277: static unsigned insert_rba PARAMS((unsigned, int, const char **));
  278: static unsigned insert_rca PARAMS((unsigned, int, const char **));
  279: static unsigned insert_za PARAMS((unsigned, int, const char **));
  280: static unsigned insert_zb PARAMS((unsigned, int, const char **));
  281: static unsigned insert_zc PARAMS((unsigned, int, const char **));
  282: static unsigned insert_bdisp PARAMS((unsigned, int, const char **));
  283: static unsigned insert_jhint PARAMS((unsigned, int, const char **));
  284: static unsigned insert_ev6hwjhint PARAMS((unsigned, int, const char **));
  285: 
  286: static int extract_rba PARAMS((unsigned, int *));
  287: static int extract_rca PARAMS((unsigned, int *));
  288: static int extract_za PARAMS((unsigned, int *));
  289: static int extract_zb PARAMS((unsigned, int *));
  290: static int extract_zc PARAMS((unsigned, int *));
  291: static int extract_bdisp PARAMS((unsigned, int *));
  292: static int extract_jhint PARAMS((unsigned, int *));
  293: static int extract_ev6hwjhint PARAMS((unsigned, int *));
  294: 
  295: ^L
  296: /* The operands table  */
  297: 
  298: const struct alpha_operand alpha_operands[] =
  299: {
  300:   /* The fields are bits, shift, insert, extract, flags */
  301:   /* The zero index is used to indicate end-of-list */
  302: #define UNUSED          0
  303:   { 0, 0, 0, 0, 0, 0 },
  304: 
  305:   /* The plain integer register fields */
  306: #define RA              (UNUSED + 1)
  307:   { 5, 21, 0, AXP_OPERAND_IR, 0, 0 },
  308: #define RB              (RA + 1)
  309:   { 5, 16, 0, AXP_OPERAND_IR, 0, 0 },
  310: #define RC              (RB + 1)
  311:   { 5, 0, 0, AXP_OPERAND_IR, 0, 0 },
  312: 
  313:   /* The plain fp register fields */
  314: #define FA              (RC + 1)
  315:   { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 },
  316: #define FB              (FA + 1)
  317:   { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 },
  318: #define FC              (FB + 1)
  319:   { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 },
  320: 
  321:   /* The integer registers when they are ZERO */
  322: #define ZA              (FC + 1)
  323:   { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za },
  324: #define ZB              (ZA + 1)
  325:   { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb },
  326: #define ZC              (ZB + 1)
  327:   { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc },
  328: 
  329:   /* The RB field when it needs parentheses */
  330: #define PRB             (ZC + 1)
  331:   { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 },
  332: 
  333:   /* The RB field when it needs parentheses _and_ a preceding comma */
  334: #define CPRB            (PRB + 1)
  335:   { 5, 16, 0,
  336:     AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 },
  337: 
  338:   /* The RB field when it must be the same as the RA field */
  339: #define RBA             (CPRB + 1)
  340:   { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba },
  341: 
  342:   /* The RC field when it must be the same as the RB field */
  343: #define RCA             (RBA + 1)
  344:   { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca },
  345: 
  346:   /* The RC field when it can *default* to RA */
  347: #define DRC1            (RCA + 1)
  348:   { 5, 0, 0,
  349:     AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
  350: 
  351:   /* The RC field when it can *default* to RB */
  352: #define DRC2            (DRC1 + 1)
  353:   { 5, 0, 0,
  354:     AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
  355: 
  356:   /* The FC field when it can *default* to RA */
  357: #define DFC1            (DRC2 + 1)
  358:   { 5, 0, 0,
  359:     AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
  360: 
  361:   /* The FC field when it can *default* to RB */
  362: #define DFC2            (DFC1 + 1)
  363:   { 5, 0, 0,
  364:     AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
  365: 
  366:   /* The unsigned 8-bit literal of Operate format insns */
  367: #define LIT             (DFC2 + 1)
  368:   { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 },
  369: 
  370:   /* The signed 16-bit displacement of Memory format insns.  From here
  371:      we can't tell what relocation should be used, so don't use a default. */
  372: #define MDISP           (LIT + 1)
  373:   { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 },
  374: 
  375:   /* The signed "23-bit" aligned displacement of Branch format insns */
  376: #define BDISP           (MDISP + 1)
  377:   { 21, 0, BFD_RELOC_23_PCREL_S2,
  378:     AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp },
  379: 
  380:   /* The 26-bit PALcode function */
  381: #define PALFN           (BDISP + 1)
  382:   { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 },
  383: 
  384:   /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */
  385: #define JMPHINT         (PALFN + 1)
  386:   { 14, 0, BFD_RELOC_ALPHA_HINT,
  387:     AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
  388:     insert_jhint, extract_jhint },
  389: 
  390:   /* The optional hint to RET/JSR_COROUTINE */
  391: #define RETHINT         (JMPHINT + 1)
  392:   { 14, 0, -RETHINT,
  393:     AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 },
  394: 
  395:   /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns */
  396: #define EV4HWDISP       (RETHINT + 1)
  397: #define EV6HWDISP       (EV4HWDISP)
  398:   { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
  399: 
  400:   /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */
  401: #define EV4HWINDEX      (EV4HWDISP + 1)
  402:   { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
  403: 
  404:   /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns
  405:      that occur in DEC PALcode.  */
  406: #define EV4EXTHWINDEX   (EV4HWINDEX + 1)
  407:   { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
  408: 
  409:   /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */
  410: #define EV5HWDISP       (EV4EXTHWINDEX + 1)
  411:   { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
  412: 
  413:   /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */
  414: #define EV5HWINDEX      (EV5HWDISP + 1)
  415:   { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
  416: 
  417:   /* The 16-bit combined index/scoreboard mask for the ev6
  418:      hw_m[ft]pr (pal19/pal1d) insns */
  419: #define EV6HWINDEX      (EV5HWINDEX + 1)
  420:   { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
  421: 
  422:   /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn */
  423: #define EV6HWJMPHINT    (EV6HWINDEX+ 1)
  424:   { 8, 0, -EV6HWJMPHINT,
  425:     AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
  426:     insert_ev6hwjhint, extract_ev6hwjhint }
  427: };
  428: 
  429: const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands);
  430: 
  431: /* The RB field when it is the same as the RA field in the same insn.
  432:    This operand is marked fake.  The insertion function just copies
  433:    the RA field into the RB field, and the extraction function just
  434:    checks that the fields are the same. */
  435: 
  436: /*ARGSUSED*/
  437: static unsigned
  438: insert_rba(insn, value, errmsg)
  439:      unsigned insn;
  440:      int value ATTRIBUTE_UNUSED;
  441:      const char **errmsg ATTRIBUTE_UNUSED;
  442: {
  443:   return insn | (((insn >> 21) & 0x1f) << 16);
  444: }
  445: 
  446: static int
  447: extract_rba(insn, invalid)
  448:      unsigned insn;
  449:      int *invalid;
  450: {
  451:   if (invalid != (int *) NULL
  452:       && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
  453:     *invalid = 1;
  454:   return 0;
  455: }
  456: 
  457: 
  458: /* The same for the RC field */
  459: 
  460: /*ARGSUSED*/
  461: static unsigned
  462: insert_rca(insn, value, errmsg)
  463:      unsigned insn;
  464:      int value ATTRIBUTE_UNUSED;
  465:      const char **errmsg ATTRIBUTE_UNUSED;
  466: {
  467:   return insn | ((insn >> 21) & 0x1f);
  468: }
  469: 
  470: static int
  471: extract_rca(insn, invalid)
  472:      unsigned insn;
  473:      int *invalid;
  474: {
  475:   if (invalid != (int *) NULL
  476:       && ((insn >> 21) & 0x1f) != (insn & 0x1f))
  477:     *invalid = 1;
  478:   return 0;
  479: }
  480: 
  481: 
  482: /* Fake arguments in which the registers must be set to ZERO */
  483: 
  484: /*ARGSUSED*/
  485: static unsigned
  486: insert_za(insn, value, errmsg)
  487:      unsigned insn;
  488:      int value ATTRIBUTE_UNUSED;
  489:      const char **errmsg ATTRIBUTE_UNUSED;
  490: {
  491:   return insn | (31 << 21);
  492: }
  493: 
  494: static int
  495: extract_za(insn, invalid)
  496:      unsigned insn;
  497:      int *invalid;
  498: {
  499:   if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31)
  500:     *invalid = 1;
  501:   return 0;
  502: }
  503: 
  504: /*ARGSUSED*/
  505: static unsigned
  506: insert_zb(insn, value, errmsg)
  507:      unsigned insn;
  508:      int value ATTRIBUTE_UNUSED;
  509:      const char **errmsg ATTRIBUTE_UNUSED;
  510: {
  511:   return insn | (31 << 16);
  512: }
  513: 
  514: static int
  515: extract_zb(insn, invalid)
  516:      unsigned insn;
  517:      int *invalid;
  518: {
  519:   if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31)
  520:     *invalid = 1;
  521:   return 0;
  522: }
  523: 
  524: /*ARGSUSED*/
  525: static unsigned
  526: insert_zc(insn, value, errmsg)
  527:      unsigned insn;
  528:      int value ATTRIBUTE_UNUSED;
  529:      const char **errmsg ATTRIBUTE_UNUSED;
  530: {
  531:   return insn | 31;
  532: }
  533: 
  534: static int
  535: extract_zc(insn, invalid)
  536:      unsigned insn;
  537:      int *invalid;
  538: {
  539:   if (invalid != (int *) NULL && (insn & 0x1f) != 31)
  540:     *invalid = 1;
  541:   return 0;
  542: }
  543: 
  544: 
  545: /* The displacement field of a Branch format insn.  */
  546: 
  547: static unsigned
  548: insert_bdisp(insn, value, errmsg)
  549:      unsigned insn;
  550:      int value;
  551:      const char **errmsg;
  552: {
  553:   if (errmsg != (const char **)NULL && (value & 3))
  554:     *errmsg = _("branch operand unaligned");
  555:   return insn | ((value / 4) & 0x1FFFFF);
  556: }
  557: 
  558: /*ARGSUSED*/
  559: static int
  560: extract_bdisp(insn, invalid)
  561:      unsigned insn;
  562:      int *invalid ATTRIBUTE_UNUSED;
  563: {
  564: