1: /* Disassembler code for CRIS.
    2:    Copyright 2000, 2001, 2002, 2004, 2005, 2006 Free Software Foundation, Inc.
    3:    Contributed by Axis Communications AB, Lund, Sweden.
    4:    Written by Hans-Peter Nilsson.
    5: 
    6:    This file is part of the GNU binutils and GDB, the GNU debugger.
    7: 
    8:    This program is free software; you can redistribute it and/or modify it
    9:    under the terms of the GNU General Public License as published by the
   10:    Free Software Foundation; either version 2, or (at your option) any later
   11:    version.
   12: 
   13:    This program is distributed in the hope that it will be useful, but WITHOUT
   14:    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   15:    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   16:    more details.
   17: 
   18:    You should have received a copy of the GNU General Public License
   19:    along with this program; if not, write to the Free Software
   20:    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
   21:    MA 02110-1301, USA.  */
   22: 
   23: #include "dis-asm.h"
   24: //#include "sysdep.h"
   25: #include "target-cris/opcode-cris.h"
   26: //#include "libiberty.h"
   27: ^L
   28: 
   29: #define FALSE 0
   30: #define TRUE 1
   31: #define CONST_STRNEQ(STR1,STR2) (strncmp ((STR1), (STR2), sizeof (STR2) - 1) == 0)
   32: 
   33: /* cris-opc.c -- Table of opcodes for the CRIS processor.
   34:    Copyright 2000, 2001, 2004 Free Software Foundation, Inc.
   35:    Contributed by Axis Communications AB, Lund, Sweden.
   36:    Originally written for GAS 1.38.1 by Mikael Asker.
   37:    Reorganized by Hans-Peter Nilsson.
   38: 
   39: This file is part of GAS, GDB and the GNU binutils.
   40: 
   41: GAS, GDB, and GNU binutils is free software; you can redistribute it
   42: and/or modify it under the terms of the GNU General Public License as
   43: published by the Free Software Foundation; either version 2, or (at your
   44: option) any later version.
   45: 
   46: GAS, GDB, and GNU binutils are distributed in the hope that they will be
   47: useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
   48: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   49: GNU General Public License for more details.
   50: 
   51: You should have received a copy of the GNU General Public License
   52: along with this program; if not, write to the Free Software
   53: Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
   54: 
   55: #ifndef NULL
   56: #define NULL (0)
   57: #endif
   58: 
   59: /* This table isn't used for CRISv32 and the size of immediate operands.  */
   60: const struct cris_spec_reg
   61: cris_spec_regs[] =
   62: {
   63:   {"bz",  0,  1, cris_ver_v32p,    NULL},
   64:   {"p0",  0,  1, 0,                NULL},
   65:   {"vr",  1,  1, 0,                NULL},
   66:   {"p1",  1,  1, 0,                NULL},
   67:   {"pid", 2,  1, cris_ver_v32p,    NULL},
   68:   {"p2",  2,  1, cris_ver_v32p,    NULL},
   69:   {"p2",  2,  1, cris_ver_warning, NULL},
   70:   {"srs", 3,  1, cris_ver_v32p,    NULL},
   71:   {"p3",  3,  1, cris_ver_v32p,    NULL},
   72:   {"p3",  3,  1, cris_ver_warning, NULL},
   73:   {"wz",  4,  2, cris_ver_v32p,    NULL},
   74:   {"p4",  4,  2, 0,                NULL},
   75:   {"ccr", 5,  2, cris_ver_v0_10,   NULL},
   76:   {"exs", 5,  4, cris_ver_v32p,    NULL},
   77:   {"p5",  5,  2, cris_ver_v0_10,   NULL},
   78:   {"p5",  5,  4, cris_ver_v32p,    NULL},
   79:   {"dcr0",6,  2, cris_ver_v0_3,    NULL},
   80:   {"eda", 6,  4, cris_ver_v32p,    NULL},
   81:   {"p6",  6,  2, cris_ver_v0_3,    NULL},
   82:   {"p6",  6,  4, cris_ver_v32p,    NULL},
   83:   {"dcr1/mof", 7, 4, cris_ver_v10p,
   84:    "Register `dcr1/mof' with ambiguous size specified.  Guessing 4 bytes"},
   85:   {"dcr1/mof", 7, 2, cris_ver_v0_3,
   86:    "Register `dcr1/mof' with ambiguous size specified.  Guessing 2 bytes"},
   87:   {"mof", 7,  4, cris_ver_v10p,    NULL},
   88:   {"dcr1",7,  2, cris_ver_v0_3,    NULL},
   89:   {"p7",  7,  4, cris_ver_v10p,    NULL},
   90:   {"p7",  7,  2, cris_ver_v0_3,    NULL},
   91:   {"dz",  8,  4, cris_ver_v32p,    NULL},
   92:   {"p8",  8,  4, 0,                NULL},
   93:   {"ibr", 9,  4, cris_ver_v0_10,   NULL},
   94:   {"ebp", 9,  4, cris_ver_v32p,    NULL},
   95:   {"p9",  9,  4, 0,                NULL},
   96:   {"irp", 10, 4, cris_ver_v0_10,   NULL},
   97:   {"erp", 10, 4, cris_ver_v32p,    NULL},
   98:   {"p10", 10, 4, 0,                NULL},
   99:   {"srp", 11, 4, 0,                NULL},
  100:   {"p11", 11, 4, 0,                NULL},
  101:   /* For disassembly use only.  Accept at assembly with a warning.  */
  102:   {"bar/dtp0", 12, 4, cris_ver_warning,
  103:    "Ambiguous register `bar/dtp0' specified"},
  104:   {"nrp", 12, 4, cris_ver_v32p,    NULL},
  105:   {"bar", 12, 4, cris_ver_v8_10,   NULL},
  106:   {"dtp0",12, 4, cris_ver_v0_3,    NULL},
  107:   {"p12", 12, 4, 0,                NULL},
  108:   /* For disassembly use only.  Accept at assembly with a warning.  */
  109:   {"dccr/dtp1",13, 4, cris_ver_warning,
  110:    "Ambiguous register `dccr/dtp1' specified"},
  111:   {"ccs", 13, 4, cris_ver_v32p,    NULL},
  112:   {"dccr",13, 4, cris_ver_v8_10,   NULL},
  113:   {"dtp1",13, 4, cris_ver_v0_3,    NULL},
  114:   {"p13", 13, 4, 0,                NULL},
  115:   {"brp", 14, 4, cris_ver_v3_10,   NULL},
  116:   {"usp", 14, 4, cris_ver_v32p,    NULL},
  117:   {"p14", 14, 4, cris_ver_v3p,     NULL},
  118:   {"usp", 15, 4, cris_ver_v10,     NULL},
  119:   {"spc", 15, 4, cris_ver_v32p,    NULL},
  120:   {"p15", 15, 4, cris_ver_v10p,    NULL},
  121:   {NULL, 0, 0, cris_ver_version_all, NULL}
  122: };
  123: 
  124: /* Add version specifiers to this table when necessary.
  125:    The (now) regular coding of register names suggests a simpler
  126:    implementation.  */
  127: const struct cris_support_reg cris_support_regs[] =
  128: {
  129:   {"s0", 0},
  130:   {"s1", 1},
  131:   {"s2", 2},
  132:   {"s3", 3},
  133:   {"s4", 4},
  134:   {"s5", 5},
  135:   {"s6", 6},
  136:   {"s7", 7},
  137:   {"s8", 8},
  138:   {"s9", 9},
  139:   {"s10", 10},
  140:   {"s11", 11},
  141:   {"s12", 12},
  142:   {"s13", 13},
  143:   {"s14", 14},
  144:   {"s15", 15},
  145:   {NULL, 0}
  146: };
  147: 
  148: /* All CRIS opcodes are 16 bits.
  149: 
  150:    - The match component is a mask saying which bits must match a
  151:      particular opcode in order for an instruction to be an instance
  152:      of that opcode.
  153: 
  154:    - The args component is a string containing characters symbolically
  155:      matching the operands of an instruction.  Used for both assembly
  156:      and disassembly.
  157: 
  158:      Operand-matching characters:
  159:      [ ] , space
  160:         Verbatim.
  161:      A  The string "ACR" (case-insensitive).
  162:      B  Not really an operand.  It causes a "BDAP -size,SP" prefix to be
  163:         output for the PUSH alias-instructions and recognizes a push-
  164:         prefix at disassembly.  This letter isn't recognized for v32.
  165:         Must be followed by a R or P letter.
  166:      !  Non-match pattern, will not match if there's a prefix insn.
  167:      b  Non-matching operand, used for branches with 16-bit
  168:         displacement. Only recognized by the disassembler.
  169:      c  5-bit unsigned immediate in bits <4:0>.
  170:      C  4-bit unsigned immediate in bits <3:0>.
  171:      d  At assembly, optionally (as in put other cases before this one)
  172:         ".d" or ".D" at the start of the operands, followed by one space
  173:         character.  At disassembly, nothing.
  174:      D  General register in bits <15:12> and <3:0>.
  175:      f  List of flags in bits <15:12> and <3:0>.
  176:      i  6-bit signed immediate in bits <5:0>.
  177:      I  6-bit unsigned immediate in bits <5:0>.
  178:      M  Size modifier (B, W or D) for CLEAR instructions.
  179:      m  Size modifier (B, W or D) in bits <5:4>
  180:      N  A 32-bit dword, like in the difference between s and y.
  181:         This has no effect on bits in the opcode.  Can also be expressed
  182:         as "[pc+]" in input.
  183:      n  As N, but PC-relative (to the start of the instruction).
  184:      o  [-128..127] word offset in bits <7:1> and <0>.  Used by 8-bit
  185:         branch instructions.
  186:      O  [-128..127] offset in bits <7:0>.  Also matches a comma and a
  187:         general register after the expression, in bits <15:12>.  Used
  188:         only for the BDAP prefix insn (in v32 the ADDOQ insn; same opcode).
  189:      P  Special register in bits <15:12>.
  190:      p  Indicates that the insn is a prefix insn.  Must be first
  191:         character.
  192:      Q  As O, but don't relax; force an 8-bit offset.
  193:      R  General register in bits <15:12>.
  194:      r  General register in bits <3:0>.
  195:      S  Source operand in bit <10> and a prefix; a 3-operand prefix
  196:         without side-effect.
  197:      s  Source operand in bits <10> and <3:0>, optionally with a
  198:         side-effect prefix, except [pc] (the name, not R15 as in ACR)
  199:         isn't allowed for v32 and higher.
  200:      T  Support register in bits <15:12>.
  201:      u  4-bit (PC-relative) unsigned immediate word offset in bits <3:0>.
  202:      U  Relaxes to either u or n, instruction is assumed LAPCQ or LAPC.
  203:         Not recognized at disassembly.
  204:      x  Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4>.
  205:      y  Like 's' but do not allow an integer at assembly.
  206:      Y  The difference s-y; only an integer is allowed.
  207:      z  Size modifier (B or W) in bit <4>.  */
  208: 
  209: 
  210: /* Please note the order of the opcodes in this table is significant.
  211:    The assembler requires that all instances of the same mnemonic must
  212:    be consecutive.  If they aren't, the assembler might not recognize
  213:    them, or may indicate an internal error.
  214: 
  215:    The disassembler should not normally care about the order of the
  216:    opcodes, but will prefer an earlier alternative if the "match-score"
  217:    (see cris-dis.c) is computed as equal.
  218: 
  219:    It should not be significant for proper execution that this table is
  220:    in alphabetical order, but please follow that convention for an easy
  221:    overview.  */
  222: 
  223: const struct cris_opcode
  224: cris_opcodes[] =
  225: {
  226:   {"abs",     0x06B0, 0x0940,             "r,R",     0, SIZE_NONE,     0,
  227:    cris_abs_op},
  228: 
  229:   {"add",     0x0600, 0x09c0,             "m r,R",   0, SIZE_NONE,     0,
  230:    cris_reg_mode_add_sub_cmp_and_or_move_op},
  231: 
  232:   {"add",     0x0A00, 0x01c0,             "m s,R",   0, SIZE_FIELD,    0,
  233:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  234: 
  235:   {"add",     0x0A00, 0x01c0,             "m S,D",   0, SIZE_NONE,
  236:    cris_ver_v0_10,
  237:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  238: 
  239:   {"add",     0x0a00, 0x05c0,             "m S,R,r", 0, SIZE_NONE,
  240:    cris_ver_v0_10,
  241:    cris_three_operand_add_sub_cmp_and_or_op},
  242: 
  243:   {"add",     0x0A00, 0x01c0,             "m s,R",   0, SIZE_FIELD,
  244:    cris_ver_v32p,
  245:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  246: 
  247:   {"addc",    0x0570, 0x0A80,             "r,R",     0, SIZE_FIX_32,
  248:    cris_ver_v32p,
  249:    cris_not_implemented_op},
  250: 
  251:   {"addc",    0x09A0, 0x0250,             "s,R",     0, SIZE_FIX_32,
  252:    cris_ver_v32p,
  253:    cris_not_implemented_op},
  254: 
  255:   {"addi",    0x0540, 0x0A80,             "x,r,A",   0, SIZE_NONE,
  256:    cris_ver_v32p,
  257:    cris_addi_op},
  258: 
  259:   {"addi",    0x0500, 0x0Ac0,             "x,r",     0, SIZE_NONE,     0,
  260:    cris_addi_op},
  261: 
  262:   /* This collates after "addo", but we want to disassemble as "addoq",
  263:      not "addo".  */
  264:   {"addoq",   0x0100, 0x0E00,             "Q,A",     0, SIZE_NONE,
  265:    cris_ver_v32p,
  266:    cris_not_implemented_op},
  267: 
  268:   {"addo",    0x0940, 0x0280,             "m s,R,A", 0, SIZE_FIELD_SIGNED,
  269:    cris_ver_v32p,
  270:    cris_not_implemented_op},
  271: 
  272:   /* This must be located after the insn above, lest we misinterpret
  273:      "addo.b -1,r0,acr" as "addo .b-1,r0,acr".  FIXME: Sounds like a
  274:      parser bug.  */
  275:   {"addo",   0x0100, 0x0E00,              "O,A",     0, SIZE_NONE,
  276:    cris_ver_v32p,
  277:    cris_not_implemented_op},
  278: 
  279:   {"addq",    0x0200, 0x0Dc0,             "I,R",     0, SIZE_NONE,     0,
  280:    cris_quick_mode_add_sub_op},
  281: 
  282:   {"adds",    0x0420, 0x0Bc0,             "z r,R",   0, SIZE_NONE,     0,
  283:    cris_reg_mode_add_sub_cmp_and_or_move_op},
  284: 
  285:   /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
  286:   {"adds",    0x0820, 0x03c0,             "z s,R",   0, SIZE_FIELD,    0,
  287:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  288: 
  289:   {"adds",    0x0820, 0x03c0,             "z S,D",   0, SIZE_NONE,
  290:    cris_ver_v0_10,
  291:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  292: 
  293:   {"adds",    0x0820, 0x07c0,             "z S,R,r", 0, SIZE_NONE,
  294:    cris_ver_v0_10,
  295:    cris_three_operand_add_sub_cmp_and_or_op},
  296: 
  297:   {"addu",    0x0400, 0x0be0,             "z r,R",   0, SIZE_NONE,     0,
  298:    cris_reg_mode_add_sub_cmp_and_or_move_op},
  299: 
  300:   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
  301:   {"addu",    0x0800, 0x03e0,             "z s,R",   0, SIZE_FIELD,    0,
  302:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  303: 
  304:   {"addu",    0x0800, 0x03e0,             "z S,D",   0, SIZE_NONE,
  305:    cris_ver_v0_10,
  306:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  307: 
  308:   {"addu",    0x0800, 0x07e0,             "z S,R,r", 0, SIZE_NONE,
  309:    cris_ver_v0_10,
  310:    cris_three_operand_add_sub_cmp_and_or_op},
  311: 
  312:   {"and",     0x0700, 0x08C0,             "m r,R",   0, SIZE_NONE,     0,
  313:    cris_reg_mode_add_sub_cmp_and_or_move_op},
  314: 
  315:   {"and",     0x0B00, 0x00C0,             "m s,R",   0, SIZE_FIELD,    0,
  316:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  317: 
  318:   {"and",     0x0B00, 0x00C0,             "m S,D",   0, SIZE_NONE,
  319:    cris_ver_v0_10,
  320:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  321: 
  322:   {"and",     0x0B00, 0x04C0,             "m S,R,r", 0, SIZE_NONE,
  323:    cris_ver_v0_10,
  324:    cris_three_operand_add_sub_cmp_and_or_op},
  325: 
  326:   {"andq",    0x0300, 0x0CC0,             "i,R",     0, SIZE_NONE,     0,
  327:    cris_quick_mode_and_cmp_move_or_op},
  328: 
  329:   {"asr",     0x0780, 0x0840,             "m r,R",   0, SIZE_NONE,     0,
  330:    cris_asr_op},
  331: 
  332:   {"asrq",    0x03a0, 0x0c40,             "c,R",     0, SIZE_NONE,     0,
  333:    cris_asrq_op},
  334: 
  335:   {"ax",      0x15B0, 0xEA4F,             "",         0, SIZE_NONE,     0,
  336:    cris_ax_ei_setf_op},
  337: 
  338:   /* FIXME: Should use branch #defines.  */
  339:   {"b",       0x0dff, 0x0200,             "b",        1, SIZE_NONE,     0,
  340:    cris_sixteen_bit_offset_branch_op},
  341: 
  342:   {"ba",
  343:    BA_QUICK_OPCODE,
  344:    0x0F00+(0xF-CC_A)*0x1000,              "o",         1, SIZE_NONE,     0,
  345:    cris_eight_bit_offset_branch_op},
  346: 
  347:   /* Needs to come after the usual "ba o", which might be relaxed to
  348:      this one.  */
  349:   {"ba",     BA_DWORD_OPCODE,
  350:    0xffff & (~BA_DWORD_OPCODE),           "n",      0, SIZE_FIX_32,
  351:    cris_ver_v32p,
  352:    cris_none_reg_mode_jump_op},
  353: 
  354:   {"bas",     0x0EBF, 0x0140,             "n,P",     0, SIZE_FIX_32,
  355:    cris_ver_v32p,
  356:    cris_none_reg_mode_jump_op},
  357: 
  358:   {"basc",     0x0EFF, 0x0100,            "n,P",     0, SIZE_FIX_32,
  359:    cris_ver_v32p,
  360:    cris_none_reg_mode_jump_op},
  361: 
  362:   {"bcc",
  363:    BRANCH_QUICK_OPCODE+CC_CC*0x1000,
  364:    0x0f00+(0xF-CC_CC)*0x1000,             "o",        1, SIZE_NONE,     0,
  365:    cris_eight_bit_offset_branch_op},
  366: 
  367:   {"bcs",
  368:    BRANCH_QUICK_OPCODE+CC_CS*0x1000,
  369:    0x0f00+(0xF-CC_CS)*0x1000,             "o",        1, SIZE_NONE,     0,
  370:    cris_eight_bit_offset_branch_op},
  371: 
  372:   {"bdap",
  373:    BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS,  "pm s,R",  0, SIZE_FIELD_SIGNED,
  374:    cris_ver_v0_10,
  375:    cris_bdap_prefix},
  376: 
  377:   {"bdap",
  378:    BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS,  "pO",      0, SIZE_NONE,
  379:    cris_ver_v0_10,
  380:    cris_quick_mode_bdap_prefix},
  381: 
  382:   {"beq",
  383:    BRANCH_QUICK_OPCODE+CC_EQ*0x1000,
  384:    0x0f00+(0xF-CC_EQ)*0x1000,             "o",        1, SIZE_NONE,     0,
  385:    cris_eight_bit_offset_branch_op},
  386: 
  387:   /* This is deliberately put before "bext" to trump it, even though not
  388:      in alphabetical order, since we don't do excluding version checks
  389:      for v0..v10.  */
  390:   {"bwf",
  391:    BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
  392:    0x0f00+(0xF-CC_EXT)*0x1000,            "o",       1, SIZE_NONE,
  393:    cris_ver_v10,
  394:    cris_eight_bit_offset_branch_op},
  395: 
  396:   {"bext",
  397:    BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
  398:    0x0f00+(0xF-CC_EXT)*0x1000,            "o",       1, SIZE_NONE,
  399:    cris_ver_v0_3,
  400:    cris_eight_bit_offset_branch_op},
  401: 
  402:   {"bge",
  403:    BRANCH_QUICK_OPCODE+CC_GE*0x1000,
  404:    0x0f00+(0xF-CC_GE)*0x1000,             "o",        1, SIZE_NONE,     0,
  405:    cris_eight_bit_offset_branch_op},
  406: 
  407:   {"bgt",
  408:    BRANCH_QUICK_OPCODE+CC_GT*0x1000,
  409:    0x0f00+(0xF-CC_GT)*0x1000,             "o",        1, SIZE_NONE,     0,
  410:    cris_eight_bit_offset_branch_op},
  411: 
  412:   {"bhi",
  413:    BRANCH_QUICK_OPCODE+CC_HI*0x1000,
  414:    0x0f00+(0xF-CC_HI)*0x1000,             "o",        1, SIZE_NONE,     0,
  415:    cris_eight_bit_offset_branch_op},
  416: 
  417:   {"bhs",
  418:    BRANCH_QUICK_OPCODE+CC_HS*0x1000,
  419:    0x0f00+(0xF-CC_HS)*0x1000,             "o",        1, SIZE_NONE,     0,
  420:    cris_eight_bit_offset_branch_op},
  421: 
  422:   {"biap", BIAP_OPCODE, BIAP_Z_BITS,      "pm r,R",  0, SIZE_NONE,
  423:    cris_ver_v0_10,
  424:    cris_biap_prefix},
  425: 
  426:   {"ble",
  427:    BRANCH_QUICK_OPCODE+CC_LE*0x1000,
  428:    0x0f00+(0xF-CC_LE)*0x1000,             "o",        1, SIZE_NONE,     0,
  429:    cris_eight_bit_offset_branch_op},
  430: 
  431:   {"blo",
  432:    BRANCH_QUICK_OPCODE+CC_LO*0x1000,
  433:    0x0f00+(0xF-CC_LO)*0x1000,             "o",        1, SIZE_NONE,     0,
  434:    cris_eight_bit_offset_branch_op},
  435: 
  436:   {"bls",
  437:    BRANCH_QUICK_OPCODE+CC_LS*0x1000,
  438:    0x0f00+(0xF-CC_LS)*0x1000,             "o",        1, SIZE_NONE,     0,
  439:    cris_eight_bit_offset_branch_op},
  440: 
  441:   {"blt",
  442:    BRANCH_QUICK_OPCODE+CC_LT*0x1000,
  443:    0x0f00+(0xF-CC_LT)*0x1000,             "o",        1, SIZE_NONE,     0,
  444:    cris_eight_bit_offset_branch_op},
  445: 
  446:   {"bmi",
  447:    BRANCH_QUICK_OPCODE+CC_MI*0x1000,
  448:    0x0f00+(0xF-CC_MI)*0x1000,             "o",        1, SIZE_NONE,     0,
  449:    cris_eight_bit_offset_branch_op},
  450: 
  451:   {"bmod",    0x0ab0, 0x0140,             "s,R",     0, SIZE_FIX_32,
  452:    cris_ver_sim_v0_10,
  453:    cris_not_implemented_op},
  454: 
  455:   {"bmod",    0x0ab0, 0x0140,             "S,D",     0, SIZE_NONE,
  456:    cris_ver_sim_v0_10,
  457:    cris_not_implemented_op},
  458: 
  459:   {"bmod",    0x0ab0, 0x0540,             "S,R,r",   0, SIZE_NONE,
  460:    cris_ver_sim_v0_10,
  461:    cris_not_implemented_op},
  462: 
  463:   {"bne",
  464:    BRANCH_QUICK_OPCODE+CC_NE*0x1000,
  465:    0x0f00+(0xF-CC_NE)*0x1000,             "o",        1, SIZE_NONE,     0,
  466:    cris_eight_bit_offset_branch_op},
  467: 
  468:   {"bound",   0x05c0, 0x0A00,             "m r,R",   0, SIZE_NONE,     0,
  469:    cris_two_operand_bound_op},
  470:   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
  471:   {"bound",   0x09c0, 0x0200,             "m s,R",   0, SIZE_FIELD,
  472:    cris_ver_v0_10,
  473:    cris_two_operand_bound_op},
  474:   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
  475:   {"bound",   0x0dcf, 0x0200,             "m Y,R",   0, SIZE_FIELD,    0,
  476:    cris_two_operand_bound_op},
  477:   {"bound",   0x09c0, 0x0200,             "m S,D",   0, SIZE_NONE,
  478:    cris_ver_v0_10,
  479:    cris_two_operand_bound_op},
  480:   {"bound",   0x09c0, 0x0600,             "m S,R,r", 0, SIZE_NONE,
  481:    cris_ver_v0_10,
  482:    cris_three_operand_bound_op},
  483: 
  484:   {"bpl",
  485:    BRANCH_QUICK_OPCODE+CC_PL*0x1000,
  486:    0x0f00+(0xF-CC_PL)*0x1000,             "o",        1, SIZE_NONE,     0,
  487:    cris_eight_bit_offset_branch_op},
  488: 
  489:   {"break",   0xe930, 0x16c0,             "C",        0, SIZE_NONE,
  490:    cris_ver_v3p,
  491:    cris_break_op},
  492: 
  493:   {"bsb",
  494:    BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
  495:    0x0f00+(0xF-CC_EXT)*0x1000,            "o",       1, SIZE_NONE,
  496:    cris_ver_v32p,
  497:    cris_eight_bit_offset_branch_op},
  498: 
  499:   {"bsr",     0xBEBF, 0x4140,             "n",        0, SIZE_FIX_32,
  500:    cris_ver_v32p,
  501:    cris_none_reg_mode_jump_op},
  502: 
  503:   {"bsrc",     0xBEFF, 0x4100,            "n",       0, SIZE_FIX_32,
  504:    cris_ver_v32p,
  505:    cris_none_reg_mode_jump_op},
  506: 
  507:   {"bstore",  0x0af0, 0x0100,             "s,R",     0, SIZE_FIX_32,
  508:    cris_ver_warning,
  509:    cris_not_implemented_op},
  510: 
  511:   {"bstore",  0x0af0, 0x0100,             "S,D",     0, SIZE_NONE,
  512:    cris_ver_warning,
  513:    cris_not_implemented_op},
  514: 
  515:   {"bstore",  0x0af0, 0x0500,             "S,R,r",   0, SIZE_NONE,
  516:    cris_ver_warning,
  517:    cris_not_implemented_op},
  518: 
  519:   {"btst",    0x04F0, 0x0B00,             "r,R",     0, SIZE_NONE,     0,
  520:    cris_btst_nop_op},
  521:   {"btstq",   0x0380, 0x0C60,             "c,R",     0, SIZE_NONE,     0,
  522:    cris_btst_nop_op},
  523: 
  524:   {"bvc",
  525:    BRANCH_QUICK_OPCODE+CC_VC*0x1000,
  526:    0x0f00+(0xF-CC_VC)*0x1000,             "o",        1, SIZE_NONE,     0,
  527:    cris_eight_bit_offset_branch_op},
  528: 
  529:   {"bvs",
  530:    BRANCH_QUICK_OPCODE+CC_VS*0x1000,
  531:    0x0f00+(0xF-CC_VS)*0x1000,             "o",        1, SIZE_NONE,     0,
  532:    cris_eight_bit_offset_branch_op},
  533: 
  534:   {"clear",   0x0670, 0x3980,             "M r",     0, SIZE_NONE,     0,
  535:    cris_reg_mode_clear_op},
  536: 
  537:   {"clear",   0x0A70, 0x3180,             "M y",     0, SIZE_NONE,     0,
  538:    cris_none_reg_mode_clear_test_op},
  539: 
  540:   {"clear",   0x0A70, 0x3180,             "M S",     0, SIZE_NONE,
  541:    cris_ver_v0_10,
  542:    cris_none_reg_mode_clear_test_op},
  543: 
  544:   {"clearf",  0x05F0, 0x0A00,             "f",        0, SIZE_NONE,     0,
  545:    cris_clearf_di_op},
  546: 
  547:   {"cmp",     0x06C0, 0x0900,             "m r,R",   0, SIZE_NONE,     0,
  548:    cris_reg_mode_add_sub_cmp_and_or_move_op},
  549: 
  550:   {"cmp",     0x0Ac0, 0x0100,             "m s,R",   0, SIZE_FIELD,    0,
  551:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  552: 
  553:   {"cmp",     0x0Ac0, 0x0100,             "m S,D",   0, SIZE_NONE,
  554:    cris_ver_v0_10,
  555:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  556: 
  557:   {"cmpq",    0x02C0, 0x0D00,             "i,R",     0, SIZE_NONE,     0,
  558:    cris_quick_mode_and_cmp_move_or_op},
  559: 
  560:   /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
  561:   {"cmps",    0x08e0, 0x0300,             "z s,R",   0, SIZE_FIELD,    0,
  562:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  563: 
  564:   {"cmps",    0x08e0, 0x0300,             "z S,D",   0, SIZE_NONE,
  565:    cris_ver_v0_10,
  566:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  567: 
  568:   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
  569:   {"cmpu",    0x08c0, 0x0320,             "z s,R" ,  0, SIZE_FIELD,    0,
  570:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  571: 
  572:   {"cmpu",    0x08c0, 0x0320,             "z S,D",   0, SIZE_NONE,
  573:    cris_ver_v0_10,
  574:    cris_none_reg_mode_add_sub