1: /*
    2:  *  APIC support
    3:  *
    4:  *  Copyright (c) 2004-2005 Fabrice Bellard
    5:  *
    6:  * This library is free software; you can redistribute it and/or
    7:  * modify it under the terms of the GNU Lesser General Public
    8:  * License as published by the Free Software Foundation; either
    9:  * version 2 of the License, or (at your option) any later version.
   10:  *
   11:  * This library is distributed in the hope that it will be useful,
   12:  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   13:  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   14:  * Lesser General Public License for more details.
   15:  *
   16:  * You should have received a copy of the GNU Lesser General Public
   17:  * License along with this library; if not, write to the Free Software
   18:  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
   19:  */
   20: #include "hw.h"
   21: #include "pc.h"
   22: #include "qemu-timer.h"
   23: 
   24: //#define DEBUG_APIC
   25: //#define DEBUG_IOAPIC
   26: 
   27: /* APIC Local Vector Table */
   28: #define APIC_LVT_TIMER   0
   29: #define APIC_LVT_THERMAL 1
   30: #define APIC_LVT_PERFORM 2
   31: #define APIC_LVT_LINT0   3
   32: #define APIC_LVT_LINT1   4
   33: #define APIC_LVT_ERROR   5
   34: #define APIC_LVT_NB      6
   35: 
   36: /* APIC delivery modes */
   37: #define APIC_DM_FIXED   0
   38: #define APIC_DM_LOWPRI  1
   39: #define APIC_DM_SMI     2
   40: #define APIC_DM_NMI     4
   41: #define APIC_DM_INIT    5
   42: #define APIC_DM_SIPI    6
   43: #define APIC_DM_EXTINT  7
   44: 
   45: /* APIC destination mode */
   46: #define APIC_DESTMODE_FLAT      0xf
   47: #define APIC_DESTMODE_CLUSTER   1
   48: 
   49: #define APIC_TRIGGER_EDGE  0
   50: #define APIC_TRIGGER_LEVEL 1
   51: 
   52: #define APIC_LVT_TIMER_PERIODIC         (1<<17)
   53: #define APIC_LVT_MASKED                 (1<<16)
   54: #define APIC_LVT_LEVEL_TRIGGER          (1<<15)
   55: #define APIC_LVT_REMOTE_IRR             (1<<14)
   56: #define APIC_INPUT_POLARITY             (1<<13)
   57: #define APIC_SEND_PENDING               (1<<12)
   58: 
   59: #define IOAPIC_NUM_PINS                 0x18
   60: 
   61: #define ESR_ILLEGAL_ADDRESS (1 << 7)
   62: 
   63: #define APIC_SV_ENABLE (1 << 8)
   64: 
   65: #define MAX_APICS 255
   66: #define MAX_APIC_WORDS 8
   67: 
   68: typedef struct APICState {
   69:     CPUState *cpu_env;
   70:     uint32_t apicbase;
   71:     uint8_t id;
   72:     uint8_t arb_id;
   73:     uint8_t tpr;
   74:     uint32_t spurious_vec;
   75:     uint8_t log_dest;
   76:     uint8_t dest_mode;
   77:     uint32_t isr[8];  /* in service register */
   78:     uint32_t tmr[8];  /* trigger mode register */
   79:     uint32_t irr[8]; /* interrupt request register */
   80:     uint32_t lvt[APIC_LVT_NB];
   81:     uint32_t esr; /* error register */
   82:     uint32_t icr[2];
   83: 
   84:     uint32_t divide_conf;
   85:     int count_shift;
   86:     uint32_t initial_count;
   87:     int64_t initial_count_load_time, next_time;
   88:     QEMUTimer *timer;
   89: } APICState;
   90: 
   91: struct IOAPICState {
   92:     uint8_t id;
   93:     uint8_t ioregsel;
   94: 
   95:     uint32_t irr;
   96:     uint64_t ioredtbl[IOAPIC_NUM_PINS];
   97: };
   98: 
   99: static int apic_io_memory;
  100: static APICState *local_apics[MAX_APICS + 1];
  101: static int last_apic_id = 0;
  102: 
  103: static void apic_init_ipi(APICState *s);
  104: static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
  105: static void apic_update_irq(APICState *s);
  106: 
  107: /* Find first bit starting from msb. Return 0 if value = 0 */
  108: static int fls_bit(uint32_t value)
  109: {
  110:     unsigned int ret = 0;
  111: 
  112: #if defined(HOST_I386)
  113:     __asm__ __volatile__ ("bsr %1, %0\n" : "+r" (ret) : "rm" (value));
  114:     return ret;
  115: #else
  116:     if (value > 0xffff)
  117:         value >>= 16, ret = 16;
  118:     if (value > 0xff)
  119:         value >>= 8, ret += 8;
  120:     if (value > 0xf)
  121:         value >>= 4, ret += 4;
  122:     if (value > 0x3)
  123:         value >>= 2, ret += 2;
  124:     return ret + (value >> 1);
  125: #endif
  126: }
  127: 
  128: /* Find first bit starting from lsb. Return 0 if value = 0 */
  129: static int ffs_bit(uint32_t value)
  130: {
  131:     unsigned int ret = 0;
  132: 
  133: #if defined(HOST_I386)
  134:     __asm__ __volatile__ ("bsf %1, %0\n" : "+r" (ret) : "rm" (value));
  135:     return ret;
  136: #else
  137:     if (!value)
  138:         return 0;
  139:     if (!(value & 0xffff))
  140:         value >>= 16, ret = 16;
  141:     if (!(value & 0xff))
  142:         value >>= 8, ret += 8;
  143:     if (!(value & 0xf))
  144:         value >>= 4, ret += 4;
  145:     if (!(value & 0x3))
  146:         value >>= 2, ret += 2;
  147:     if (!(value & 0x1))
  148:         ret++;
  149:     return ret;
  150: #endif
  151: }
  152: 
  153: static inline void set_bit(uint32_t *tab, int index)
  154: {
  155:     int i, mask;
  156:     i = index >> 5;
  157:     mask = 1 << (index & 0x1f);
  158:     tab[i] |= mask;
  159: }
  160: 
  161: static inline void reset_bit(uint32_t *tab, int index)
  162: {
  163:     int i, mask;
  164:     i = index >> 5;
  165:     mask = 1 << (index & 0x1f);
  166:     tab[i] &= ~mask;
  167: }
  168: 
  169: #define foreach_apic(apic, deliver_bitmask, code) \
  170: {\
  171:     int __i, __j, __mask;\
  172:     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
  173:         __mask = deliver_bitmask[__i];\
  174:         if (__mask) {\
  175:             for(__j = 0; __j < 32; __j++) {\
  176:                 if (__mask & (1 << __j)) {\
  177:                     apic = local_apics[__i * 32 + __j];\
  178:                     if (apic) {\
  179:                         code;\
  180:                     }\
  181:                 }\
  182:             }\
  183:         }\
  184:     }\
  185: }
  186: 
  187: static void apic_bus_deliver(const uint32_t *deliver_bitmask,
  188:                              uint8_t delivery_mode,
  189:                              uint8_t vector_num, uint8_t polarity,
  190:                              uint8_t trigger_mode)
  191: {
  192:     APICState *apic_iter;
  193: 
  194:     switch (delivery_mode) {
  195:         case APIC_DM_LOWPRI:
  196:             /* XXX: search for focus processor, arbitration */
  197:             {
  198:                 int i, d;
  199:                 d = -1;
  200:                 for(i = 0; i < MAX_APIC_WORDS; i++) {
  201:                     if (deliver_bitmask[i]) {
  202:                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
  203:                         break;
  204:                     }
  205:                 }
  206:                 if (d >= 0) {
  207:                     apic_iter = local_apics[d];
  208:                     if (apic_iter) {
  209:                         apic_set_irq(apic_iter, vector_num, trigger_mode);
  210:                     }
  211:                 }
  212:             }
  213:             return;
  214: 
  215:         case APIC_DM_FIXED:
  216:             break;
  217: 
  218:         case APIC_DM_SMI:
  219:         case APIC_DM_NMI:
  220:             break;
  221: 
  222:         case APIC_DM_INIT:
  223:             /* normal INIT IPI sent to processors */
  224:             foreach_apic(apic_iter, deliver_bitmask,
  225:                          apic_init_ipi(apic_iter) );
  226:             return;
  227: 
  228:         case APIC_DM_EXTINT:
  229:             /* handled in I/O APIC code */
  230:             break;
  231: 
  232:         default:
  233:             return;
  234:     }
  235: 
  236:     foreach_apic(apic_iter, deliver_bitmask,
  237:                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
  238: }
  239: 
  240: void cpu_set_apic_base(CPUState *env, uint64_t val)
  241: {
  242:     APICState *s = env->apic_state;
  243: #ifdef DEBUG_APIC
  244:     printf("cpu_set_apic_base: %016" PRIx64 "\n", val);
  245: #endif
  246:     s->apicbase = (val & 0xfffff000) |
  247:         (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
  248:     /* if disabled, cannot be enabled again */
  249:     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
  250:         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
  251:         env->cpuid_features &= ~CPUID_APIC;
  252:         s->spurious_vec &= ~APIC_SV_ENABLE;
  253:     }
  254: }
  255: 
  256: uint64_t cpu_get_apic_base(CPUState *env)
  257: {
  258:     APICState *s = env->apic_state;
  259: #ifdef DEBUG_APIC
  260:     printf("cpu_get_apic_base: %016" PRIx64 "\n", (uint64_t)s->apicbase);
  261: #endif
  262:     return s->apicbase;
  263: }
  264: 
  265: void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
  266: {
  267:     APICState *s = env->apic_state;
  268:     s->tpr = (val & 0x0f) << 4;
  269:     apic_update_irq(s);
  270: }
  271: 
  272: uint8_t cpu_get_apic_tpr(CPUX86State *env)
  273: {
  274:     APICState *s = env->apic_state;
  275:     return s->tpr >> 4;
  276: }
  277: 
  278: /* return -1 if no bit is set */
  279: static int get_highest_priority_int(uint32_t *tab)
  280: {
  281:     int i;
  282:     for(i = 7; i >= 0; i--) {
  283:         if (tab[i] != 0) {
  284:             return i * 32 + fls_bit(tab[i]);
  285:         }
  286:     }
  287:     return -1;
  288: }
  289: 
  290: static int apic_get_ppr(APICState *s)
  291: {
  292:     int tpr, isrv, ppr;
  293: 
  294:     tpr = (s->tpr >> 4);
  295:     isrv = get_highest_priority_int(s->isr);
  296:     if (isrv < 0)
  297:         isrv = 0;
  298:     isrv >>= 4;
  299:     if (tpr >= isrv)
  300:         ppr = s->tpr;
  301:     else
  302:         ppr = isrv << 4;
  303:     return ppr;
  304: }
  305: 
  306: static int apic_get_arb_pri(APICState *s)
  307: {
  308:     /* XXX: arbitration */
  309:     return 0;
  310: }
  311: 
  312: /* signal the CPU if an irq is pending */
  313: static void apic_update_irq(APICState *s)
  314: {
  315:     int irrv, ppr;
  316:     if (!(s->spurious_vec & APIC_SV_ENABLE))
  317:         return;
  318:     irrv = get_highest_priority_int(s->irr);
  319:     if (irrv < 0)
  320:         return;
  321:     ppr = apic_get_ppr(s);
  322:     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
  323:         return;
  324:     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
  325: }
  326: 
  327: static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
  328: {
  329:     set_bit(s->irr, vector_num);
  330:     if (trigger_mode)
  331:         set_bit(s->tmr, vector_num);
  332:     else
  333:         reset_bit(s->tmr, vector_num);
  334:     apic_update_irq(s);
  335: }
  336: 
  337: static void apic_eoi(APICState *s)
  338: {
  339:     int isrv;
  340:     isrv = get_highest_priority_int(s->isr);
  341:     if (isrv < 0)
  342:         return;
  343:     reset_bit(s->isr, isrv);
  344:     /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
  345:             set the remote IRR bit for level triggered interrupts. */
  346:     apic_update_irq(s);
  347: }
  348: 
  349: static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
  350:                                       uint8_t dest, uint8_t dest_mode)
  351: {
  352:     APICState *apic_iter;
  353:     int i;
  354: 
  355:     if (dest_mode == 0) {
  356:         if (dest == 0xff) {
  357:             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
  358:         } else {
  359:             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
  360:             set_bit(deliver_bitmask, dest);
  361:         }
  362:     } else {
  363:         /* XXX: cluster mode */
  364:         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
  365:         for(i = 0; i < MAX_APICS; i++) {
  366:             apic_iter = local_apics[i];
  367:             if (apic_iter) {
  368:                 if (apic_iter->dest_mode == 0xf) {
  369:                     if (dest & apic_iter->log_dest)
  370:                         set_bit(deliver_bitmask, i);
  371:                 } else if (apic_iter->dest_mode == 0x0) {
  372:                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
  373:                         (dest & apic_iter->log_dest & 0x0f)) {
  374:                         set_bit(deliver_bitmask, i);
  375:                     }
  376:                 }
  377:             }
  378:         }
  379:     }
  380: }
  381: 
  382: 
  383: static void apic_init_ipi(APICState *s)
  384: {
  385:     int i;
  386: 
  387:     s->tpr = 0;
  388:     s->spurious_vec = 0xff;
  389:     s->log_dest = 0;
  390:     s->dest_mode = 0xf;
  391:     memset(s->isr, 0, sizeof(s->isr));
  392:     memset(s->tmr, 0, sizeof(s->tmr));
  393:     memset(s->irr, 0, sizeof(s->irr));
  394:     for(i = 0; i < APIC_LVT_NB; i++)
  395:         s->lvt[i] = 1 << 16; /* mask LVT */
  396:     s->esr = 0;
  397:     memset(s->icr, 0, sizeof(s->icr));
  398:     s->divide_conf = 0;
  399:     s->count_shift = 0;
  400:     s->initial_count = 0;
  401:     s->initial_count_load_time = 0;
  402:     s->next_time = 0;
  403: }
  404: 
  405: /* send a SIPI message to the CPU to start it */
  406: static void apic_startup(APICState *s, int vector_num)
  407: {
  408:     CPUState *env = s->cpu_env;
  409:     if (!(env->hflags & HF_HALTED_MASK))
  410:         return;
  411:     env->eip = 0;
  412:     cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
  413:                            0xffff, 0);
  414:     env->hflags &= ~HF_HALTED_MASK;
  415: }
  416: 
  417: static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
  418:                          uint8_t delivery_mode, uint8_t vector_num,
  419:                          uint8_t polarity, uint8_t trigger_mode)
  420: {
  421:     uint32_t deliver_bitmask[MAX_APIC_WORDS];
  422:     int dest_shorthand = (s->icr[0] >> 18) & 3;
  423:     APICState *apic_iter;
  424: 
  425:     switch (dest_shorthand) {
  426:     case 0:
  427:         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
  428:         break;
  429:     case 1:
  430:         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
  431:         set_bit(deliver_bitmask, s->id);
  432:         break;
  433:     case 2:
  434:         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
  435:         break;
  436:     case 3:
  437:         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
  438:         reset_bit(deliver_bitmask, s->id);
  439:         break;
  440:     }
  441: 
  442:     switch (delivery_mode) {
  443:         case APIC_DM_INIT:
  444:             {
  445:                 int trig_mode = (s->icr[0] >> 15) & 1;
  446:                 int level = (s->icr[0] >> 14) & 1;
  447:                 if (level == 0 && trig_mode == 1) {
  448:                     foreach_apic(apic_iter, deliver_bitmask,
  449:                                  apic_iter->arb_id = apic_iter->id );
  450:                     return;
  451:                 }
  452:             }
  453:             break;
  454: 
  455:         case APIC_DM_SIPI:
  456:             foreach_apic(apic_iter, deliver_bitmask,
  457:                          apic_startup(apic_iter, vector_num) );
  458:             return;
  459:     }
  460: 
  461:     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
  462:                      trigger_mode);
  463: }
  464: 
  465: int apic_get_interrupt(CPUState *env)
  466: {
  467:     APICState *s = env->apic_state;
  468:     int intno;
  469: 
  470:     /* if the APIC is installed or enabled, we let the 8259 handle the
  471:        IRQs */
  472:     if (!s)
  473:         return -1;
  474:     if (!(s->spurious_vec & APIC_SV_ENABLE))
  475:         return -1;
  476: 
  477:     /* XXX: spurious IRQ handling */
  478:     intno = get_highest_priority_int(s->irr);
  479:     if (intno < 0)
  480:         return -1;
  481:     if (s->tpr && intno <= s->tpr)
  482:         return s->spurious_vec & 0xff;
  483:     reset_bit(s->irr, intno);
  484:     set_bit(s->isr, intno);
  485:     apic_update_irq(s);
  486:     return intno;
  487: }
  488: 
  489: int apic_accept_pic_intr(CPUState *env)
  490: {
  491:     APICState *s = env->apic_state;
  492:     uint32_t lvt0;
  493: 
  494:     if (!s)
  495:         return -1;
  496: 
  497:     lvt0 = s->lvt[APIC_LVT_LINT0];
  498: 
  499:     if (s->id == 0 &&
  500:         ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
  501:          ((lvt0 & APIC_LVT_MASKED) == 0 &&
  502:           ((lvt0 >> 8) & 0x7) == APIC_DM_EXTINT)))
  503:         return 1;
  504: 
  505:     return 0;
  506: }
  507: 
  508: static uint32_t apic_get_current_count(APICState *s)
  509: {
  510:     int64_t d;
  511:     uint32_t val;
  512:     d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
  513:         s->count_shift;
  514:     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
  515:         /* periodic */
  516:         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
  517:     } else {
  518:         if (d >= s->initial_count)
  519:             val = 0;
  520:         else
  521:             val = s->initial_count - d;
  522:     }
  523:     return val;
  524: }
  525: 
  526: static void apic_timer_update(APICState *s, int64_t current_time)
  527: {
  528:     int64_t next_time, d;
  529: 
  530:     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
  531:         d = (current_time - s->initial_count_load_time) >>
  532:             s->count_shift;
  533:         if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
  534:             d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
  535:         } else {
  536:             if (d >= s->initial_count)
  537:                 goto no_timer;
  538:             d = (uint64_t)s->initial_count + 1;
  539:         }
  540:         next_time = s->initial_count_load_time + (d << s->count_shift);
  541:         qemu_mod_timer(s->timer, next_time);
  542:         s->next_time = next_time;
  543:     } else {
  544:     no_timer:
  545:         qemu_del_timer(s->timer);
  546:     }
  547: }
  548: 
  549: static void apic_timer(void *opaque)
  550: {
  551:     APICState *s = opaque;
  552: 
  553:     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
  554:         apic_set_irq(s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
  555:     }
  556:     apic_timer_update(s, s->next_time);
  557: }
  558: 
  559: static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
  560: {
  561:     return 0;
  562: }
  563: 
  564: static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
  565: {
  566:     return 0;
  567: }
  568: 
  569: static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
  570: {
  571: }
  572: 
  573: static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
  574: {
  575: }
  576: 
  577: static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
  578: {
  579:     CPUState *env;
  580:     APICState *s;
  581:     uint32_t val;
  582:     int index;
  583: 
  584:     env = cpu_single_env;
  585:     if (!env)
  586:         return 0;