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24: #include <time.h>
25: #include <sys/time.h>
26: #include "hw.h"
27: #include "sysemu.h"
28: #include "boards.h"
29:
30: extern FILE *logfile;
31:
32: static void main_cpu_reset(void *opaque)
33: {
34: CPUState *env = opaque;
35: cpu_reset(env);
36: }
37:
38: static uint32_t fs_mmio_readb (void *opaque, target_phys_addr_t addr)
39: {
40: CPUState *env = opaque;
41: uint32_t r = 0;
42: printf ("%s %x pc=%x\n", __func__, addr, env->pc);
43: return r;
44: }
45: static uint32_t fs_mmio_readw (void *opaque, target_phys_addr_t addr)
46: {
47: CPUState *env = opaque;
48: uint32_t r = 0;
49: printf ("%s %x pc=%x\n", __func__, addr, env->pc);
50: return r;
51: }
52:
53: static uint32_t fs_mmio_readl (void *opaque, target_phys_addr_t addr)
54: {
55: CPUState *env = opaque;
56: uint32_t r = 0;
57: printf ("%s %x p=%x\n", __func__, addr, env->pc);
58: return r;
59: }
60:
61: static void
62: fs_mmio_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
63: {
64: CPUState *env = opaque;
65: printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc);
66: }
67: static void
68: fs_mmio_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
69: {
70: CPUState *env = opaque;
71: printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc);
72: }
73: static void
74: fs_mmio_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
75: {
76: CPUState *env = opaque;
77: printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc);
78: }
79:
80: static CPUReadMemoryFunc *fs_mmio_read[] = {
81: &fs_mmio_readb,
82: &fs_mmio_readw,
83: &fs_mmio_readl,
84: };
85:
86: static CPUWriteMemoryFunc *fs_mmio_write[] = {
87: &fs_mmio_writeb,
88: &fs_mmio_writew,
89: &fs_mmio_writel,
90: };
91:
92:
93:
94: extern void etraxfs_timer_init(CPUState *env, qemu_irq *irqs);
95: extern void etraxfs_ser_init(CPUState *env, qemu_irq *irqs);
96:
97: void etrax_ack_irq(CPUState *env, uint32_t mask)
98: {
99: env->pending_interrupts &= ~mask;
100: }
101:
102: static void dummy_cpu_set_irq(void *opaque, int irq, int level)
103: {
104: CPUState *env = opaque;
105:
106:
107: env->pending_interrupts |= 1 << irq;
108: cpu_interrupt(env, CPU_INTERRUPT_HARD);
109: }
110:
111: static
112: void bareetraxfs_init (int ram_size, int vga_ram_size,
113: const char *boot_device, DisplayState *ds,
114: const char *kernel_filename, const char *kernel_cmdline,
115: const char *initrd_filename, const char *cpu_model)
116: {
117: CPUState *env;
118: qemu_irq *irqs;
119: int kernel_size;
120: int internal_regs;
121:
122:
123: if (cpu_model == NULL) {
124: cpu_model = "crisv32";
125: }
126: env = cpu_init(cpu_model);
127:
128: qemu_register_reset(main_cpu_reset, env);
129: irqs = qemu_allocate_irqs(dummy_cpu_set_irq, env, 32);
130:
131: internal_regs = cpu_register_io_memory(0,
132: fs_mmio_read, fs_mmio_write, env);
133:
134: cpu_register_physical_memory (0xac000000, 0x4010000, internal_regs);
135:
136: cpu_register_physical_memory(0x40000000, ram_size, IO_MEM_RAM);
137:
138: etraxfs_timer_init(env, irqs);
139: etraxfs_ser_init(env, irqs);
140:
141: kernel_size = load_image(kernel_filename, phys_ram_base + 0x4000);
142:
143: env->regs[8] = 0x56902387;
144: env->regs[9] = 0x40004000 + kernel_size;
145: env->pc = 0x40004000;
146:
147: {
148: unsigned char *ptr = phys_ram_base + 0x4000;
149: int i;
150: for (i = 0; i < 8; i++)
151: {
152: printf ("%2.2x ", ptr[i]);
153: }
154: printf("\n");
155: }
156:
157: printf ("pc =%x\n", env->pc);
158: printf ("ram size =%d\n", ram_size);
159: printf ("kernel name =%s\n", kernel_filename);
160: printf ("kernel size =%d\n", kernel_size);
161: printf ("cpu haltd =%d\n", env->halted);
162: }
163:
164: void DMA_run(void)
165: {
166: }
167:
168: void pic_info()
169: {
170: }
171:
172: void irq_info()
173: {
174: }
175:
176: QEMUMachine bareetraxfs_machine = {
177: "bareetraxfs",
178: "Bare ETRAX FS board",
179: bareetraxfs_init,
180: };