1: /*
    2:  * QEMU ETRAX System Emulator
    3:  *
    4:  * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
    5:  *
    6:  * Permission is hereby granted, free of charge, to any person obtaining a copy
    7:  * of this software and associated documentation files (the "Software"), to deal
    8:  * in the Software without restriction, including without limitation the rights
    9:  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   10:  * copies of the Software, and to permit persons to whom the Software is
   11:  * furnished to do so, subject to the following conditions:
   12:  *
   13:  * The above copyright notice and this permission notice shall be included in
   14:  * all copies or substantial portions of the Software.
   15:  *
   16:  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   17:  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   18:  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
   19:  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   20:  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
   21:  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
   22:  * THE SOFTWARE.
   23:  */
   24: 
   25: #include <stdio.h>
   26: #include <ctype.h>
   27: #include "hw.h"
   28: 
   29: #define RW_TR_DMA_EN 0xb0026004
   30: #define RW_DOUT 0xb002601c
   31: #define RW_STAT_DIN 0xb0026020
   32: #define R_STAT_DIN 0xb0026024
   33: 
   34: static uint32_t ser_readb (void *opaque, target_phys_addr_t addr)
   35: {
   36:         CPUState *env = opaque;
   37:         uint32_t r = 0;
   38:         printf ("%s %x pc=%x\n", __func__, addr, env->pc);
   39:         return r;
   40: }
   41: static uint32_t ser_readw (void *opaque, target_phys_addr_t addr)
   42: {
   43:         CPUState *env = opaque;
   44:         uint32_t r = 0;
   45:         printf ("%s %x pc=%x\n", __func__, addr, env->pc);
   46:         return r;
   47: }
   48: 
   49: static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
   50: {
   51:         CPUState *env = opaque;
   52:         uint32_t r = 0;
   53: 
   54:         switch (addr)
   55:         {
   56:                 case RW_TR_DMA_EN:
   57:                         break;
   58:                 case R_STAT_DIN:
   59:                         r |= 1 << 24; /* set tr_rdy.  */
   60:                         r |= 1 << 22; /* set tr_idle.  */
   61:                         break;
   62: 
   63:                 default:
   64:                         printf ("%s %x p=%x\n", __func__, addr, env->pc);
   65:                         break;
   66:         }
   67:         return r;
   68: }
   69: 
   70: static void
   71: ser_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
   72: {
   73:         CPUState *env = opaque;
   74:         printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc);
   75: }
   76: static void
   77: ser_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
   78: {
   79:         CPUState *env = opaque;
   80:         printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc);
   81: }
   82: static void
   83: ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
   84: {
   85:         CPUState *env = opaque;
   86: 
   87:         switch (addr)
   88:         {
   89:                 case RW_TR_DMA_EN:
   90:                         break;
   91:                 case RW_DOUT:
   92:                         if (isprint(value) || isspace(value))
   93:                                 putchar(value);
   94:                         else
   95:                                 putchar('.');
   96:                         break;
   97:                 default:
   98:                         printf ("%s %x %x pc=%x\n",
   99:                                 __func__, addr, value, env->pc);
  100:                         break;
  101:         }
  102: }
  103: 
  104: static CPUReadMemoryFunc *ser_read[] = {
  105:     &ser_readb,
  106:     &ser_readw,
  107:     &ser_readl,
  108: };
  109: 
  110: static CPUWriteMemoryFunc *ser_write[] = {
  111:     &ser_writeb,
  112:     &ser_writew,
  113:     &ser_writel,
  114: };
  115: 
  116: void etraxfs_ser_init(CPUState *env, qemu_irq *irqs)
  117: {
  118:         int ser_regs;
  119: 
  120:         ser_regs = cpu_register_io_memory(0, ser_read, ser_write, env);
  121:         cpu_register_physical_memory (0xb0026000, 0x3c, ser_regs);
  122: }