1: /*
    2:  * QEMU GT64120 PCI host
    3:  *
    4:  * Copyright (c) 2006,2007 Aurelien Jarno
    5:  *
    6:  * Permission is hereby granted, free of charge, to any person obtaining a copy
    7:  * of this software and associated documentation files (the "Software"), to deal
    8:  * in the Software without restriction, including without limitation the rights
    9:  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   10:  * copies of the Software, and to permit persons to whom the Software is
   11:  * furnished to do so, subject to the following conditions:
   12:  *
   13:  * The above copyright notice and this permission notice shall be included in
   14:  * all copies or substantial portions of the Software.
   15:  *
   16:  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   17:  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   18:  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
   19:  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   20:  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
   21:  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
   22:  * THE SOFTWARE.
   23:  */
   24: 
   25: #include "hw.h"
   26: #include "mips.h"
   27: #include "pci.h"
   28: #include "pc.h"
   29: 
   30: typedef target_phys_addr_t pci_addr_t;
   31: #include "pci_host.h"
   32: 
   33: //#define DEBUG
   34: 
   35: #ifdef DEBUG
   36: #define dprintf(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
   37: #else
   38: #define dprintf(fmt, ...)
   39: #endif
   40: 
   41: #define GT_REGS                 (0x1000 >> 2)
   42: 
   43: /* CPU Configuration */
   44: #define GT_CPU                  (0x000 >> 2)
   45: #define GT_MULTI                (0x120 >> 2)
   46: 
   47: /* CPU Address Decode */
   48: #define GT_SCS10LD              (0x008 >> 2)
   49: #define GT_SCS10HD              (0x010 >> 2)
   50: #define GT_SCS32LD              (0x018 >> 2)
   51: #define GT_SCS32HD              (0x020 >> 2)
   52: #define GT_CS20LD               (0x028 >> 2)
   53: #define GT_CS20HD               (0x030 >> 2)
   54: #define GT_CS3BOOTLD            (0x038 >> 2)
   55: #define GT_CS3BOOTHD            (0x040 >> 2)
   56: #define GT_PCI0IOLD             (0x048 >> 2)
   57: #define GT_PCI0IOHD             (0x050 >> 2)
   58: #define GT_PCI0M0LD             (0x058 >> 2)
   59: #define GT_PCI0M0HD             (0x060 >> 2)
   60: #define GT_PCI0M1LD             (0x080 >> 2)
   61: #define GT_PCI0M1HD             (0x088 >> 2)
   62: #define GT_PCI1IOLD             (0x090 >> 2)
   63: #define GT_PCI1IOHD             (0x098 >> 2)
   64: #define GT_PCI1M0LD             (0x0a0 >> 2)
   65: #define GT_PCI1M0HD             (0x0a8 >> 2)
   66: #define GT_PCI1M1LD             (0x0b0 >> 2)
   67: #define GT_PCI1M1HD             (0x0b8 >> 2)
   68: #define GT_ISD                  (0x068 >> 2)
   69: 
   70: #define GT_SCS10AR              (0x0d0 >> 2)
   71: #define GT_SCS32AR              (0x0d8 >> 2)
   72: #define GT_CS20R                (0x0e0 >> 2)
   73: #define GT_CS3BOOTR             (0x0e8 >> 2)
   74: 
   75: #define GT_PCI0IOREMAP          (0x0f0 >> 2)
   76: #define GT_PCI0M0REMAP          (0x0f8 >> 2)
   77: #define GT_PCI0M1REMAP          (0x100 >> 2)
   78: #define GT_PCI1IOREMAP          (0x108 >> 2)
   79: #define GT_PCI1M0REMAP          (0x110 >> 2)
   80: #define GT_PCI1M1REMAP          (0x118 >> 2)
   81: 
   82: /* CPU Error Report */
   83: #define GT_CPUERR_ADDRLO        (0x070 >> 2)
   84: #define GT_CPUERR_ADDRHI        (0x078 >> 2)
   85: #define GT_CPUERR_DATALO        (0x128 >> 2)               /* GT-64120A only  */
   86: #define GT_CPUERR_DATAHI        (0x130 >> 2)               /* GT-64120A only  */
   87: #define GT_CPUERR_PARITY        (0x138 >> 2)               /* GT-64120A only  */
   88: 
   89: /* CPU Sync Barrier */
   90: #define GT_PCI0SYNC             (0x0c0 >> 2)
   91: #define GT_PCI1SYNC             (0x0c8 >> 2)
   92: 
   93: /* SDRAM and Device Address Decode */
   94: #define GT_SCS0LD               (0x400 >> 2)
   95: #define GT_SCS0HD               (0x404 >> 2)
   96: #define GT_SCS1LD               (0x408 >> 2)
   97: #define GT_SCS1HD               (0x40c >> 2)
   98: #define GT_SCS2LD               (0x410 >> 2)
   99: #define GT_SCS2HD               (0x414 >> 2)
  100: #define GT_SCS3LD               (0x418 >> 2)
  101: #define GT_SCS3HD               (0x41c >> 2)
  102: #define GT_CS0LD                (0x420 >> 2)
  103: #define GT_CS0HD                (0x424 >> 2)
  104: #define GT_CS1LD                (0x428 >> 2)
  105: #define GT_CS1HD                (0x42c >> 2)
  106: #define GT_CS2LD                (0x430 >> 2)
  107: #define GT_CS2HD                (0x434 >> 2)
  108: #define GT_CS3LD                (0x438 >> 2)
  109: #define GT_CS3HD                (0x43c >> 2)
  110: #define GT_BOOTLD               (0x440 >> 2)
  111: #define GT_BOOTHD               (0x444 >> 2)
  112: #define GT_ADERR                (0x470 >> 2)
  113: 
  114: /* SDRAM Configuration */
  115: #define GT_SDRAM_CFG            (0x448 >> 2)
  116: #define GT_SDRAM_OPMODE         (0x474 >> 2)
  117: #define GT_SDRAM_BM             (0x478 >> 2)
  118: #define GT_SDRAM_ADDRDECODE     (0x47c >> 2)
  119: 
  120: /* SDRAM Parameters */
  121: #define GT_SDRAM_B0             (0x44c >> 2)
  122: #define GT_SDRAM_B1             (0x450 >> 2)
  123: #define GT_SDRAM_B2             (0x454 >> 2)
  124: #define GT_SDRAM_B3             (0x458 >> 2)
  125: 
  126: /* Device Parameters */
  127: #define GT_DEV_B0               (0x45c >> 2)
  128: #define GT_DEV_B1               (0x460 >> 2)
  129: #define GT_DEV_B2               (0x464 >> 2)
  130: #define GT_DEV_B3               (0x468 >> 2)
  131: #define GT_DEV_BOOT             (0x46c >> 2)
  132: 
  133: /* ECC */
  134: #define GT_ECC_ERRDATALO        (0x480 >> 2)           /* GT-64120A only  */
  135: #define GT_ECC_ERRDATAHI        (0x484 >> 2)           /* GT-64120A only  */
  136: #define GT_ECC_MEM              (0x488 >> 2)                /* GT-64120A only  */
  137: #define GT_ECC_CALC             (0x48c >> 2)               /* GT-64120A only  */
  138: #define GT_ECC_ERRADDR          (0x490 >> 2)            /* GT-64120A only  */
  139: 
  140: /* DMA Record */
  141: #define GT_DMA0_CNT             (0x800 >> 2)
  142: #define GT_DMA1_CNT             (0x804 >> 2)
  143: #define GT_DMA2_CNT             (0x808 >> 2)
  144: #define GT_DMA3_CNT             (0x80c >> 2)
  145: #define GT_DMA0_SA              (0x810 >> 2)
  146: #define GT_DMA1_SA              (0x814 >> 2)
  147: #define GT_DMA2_SA              (0x818 >> 2)
  148: #define GT_DMA3_SA              (0x81c >> 2)
  149: #define GT_DMA0_DA              (0x820 >> 2)
  150: #define GT_DMA1_DA              (0x824 >> 2)
  151: #define GT_DMA2_DA              (0x828 >> 2)
  152: #define GT_DMA3_DA              (0x82c >> 2)
  153: #define GT_DMA0_NEXT            (0x830 >> 2)
  154: #define GT_DMA1_NEXT            (0x834 >> 2)
  155: #define GT_DMA2_NEXT            (0x838 >> 2)
  156: #define GT_DMA3_NEXT            (0x83c >> 2)
  157: #define GT_DMA0_CUR             (0x870 >> 2)
  158: #define GT_DMA1_CUR             (0x874 >> 2)
  159: #define GT_DMA2_CUR             (0x878 >> 2)
  160: #define GT_DMA3_CUR             (0x87c >> 2)
  161: 
  162: /* DMA Channel Control */
  163: #define GT_DMA0_CTRL            (0x840 >> 2)
  164: #define GT_DMA1_CTRL            (0x844 >> 2)
  165: #define GT_DMA2_CTRL            (0x848 >> 2)
  166: #define GT_DMA3_CTRL            (0x84c >> 2)
  167: 
  168: /* DMA Arbiter */
  169: #define GT_DMA_ARB              (0x860 >> 2)
  170: 
  171: /* Timer/Counter */
  172: #define GT_TC0                  (0x850 >> 2)
  173: #define GT_TC1                  (0x854 >> 2)
  174: #define GT_TC2                  (0x858 >> 2)
  175: #define GT_TC3                  (0x85c >> 2)
  176: #define GT_TC_CONTROL           (0x864 >> 2)
  177: 
  178: /* PCI Internal */
  179: #define GT_PCI0_CMD             (0xc00 >> 2)
  180: #define GT_PCI0_TOR             (0xc04 >> 2)
  181: #define GT_PCI0_BS_SCS10        (0xc08 >> 2)
  182: #define GT_PCI0_BS_SCS32        (0xc0c >> 2)
  183: #define GT_PCI0_BS_CS20         (0xc10 >> 2)
  184: #define GT_PCI0_BS_CS3BT        (0xc14 >> 2)
  185: #define GT_PCI1_IACK            (0xc30 >> 2)
  186: #define GT_PCI0_IACK            (0xc34 >> 2)
  187: #define GT_PCI0_BARE            (0xc3c >> 2)
  188: #define GT_PCI0_PREFMBR         (0xc40 >> 2)
  189: #define GT_PCI0_SCS10_BAR       (0xc48 >> 2)
  190: #define GT_PCI0_SCS32_BAR       (0xc4c >> 2)
  191: #define GT_PCI0_CS20_BAR        (0xc50 >> 2)
  192: #define GT_PCI0_CS3BT_BAR       (0xc54 >> 2)
  193: #define GT_PCI0_SSCS10_BAR      (0xc58 >> 2)
  194: #define GT_PCI0_SSCS32_BAR      (0xc5c >> 2)
  195: #define GT_PCI0_SCS3BT_BAR      (0xc64 >> 2)
  196: #define GT_PCI1_CMD             (0xc80 >> 2)
  197: #define GT_PCI1_TOR             (0xc84 >> 2)
  198: #define GT_PCI1_BS_SCS10        (0xc88 >> 2)
  199: #define GT_PCI1_BS_SCS32        (0xc8c >> 2)
  200: #define GT_PCI1_BS_CS20         (0xc90 >> 2)
  201: #define GT_PCI1_BS_CS3BT        (0xc94 >> 2)
  202: #define GT_PCI1_BARE            (0xcbc >> 2)
  203: #define GT_PCI1_PREFMBR         (0xcc0 >> 2)
  204: #define GT_PCI1_SCS10_BAR       (0xcc8 >> 2)
  205: #define GT_PCI1_SCS32_BAR       (0xccc >> 2)
  206: #define GT_PCI1_CS20_BAR        (0xcd0 >> 2)
  207: #define GT_PCI1_CS3BT_BAR       (0xcd4 >> 2)
  208: #define GT_PCI1_SSCS10_BAR      (0xcd8 >> 2)
  209: #define GT_PCI1_SSCS32_BAR      (0xcdc >> 2)
  210: #define GT_PCI1_SCS3BT_BAR      (0xce4 >> 2)
  211: #define GT_PCI1_CFGADDR         (0xcf0 >> 2)
  212: #define GT_PCI1_CFGDATA         (0xcf4 >> 2)
  213: #define GT_PCI0_CFGADDR         (0xcf8 >> 2)
  214: #define GT_PCI0_CFGDATA         (0xcfc >> 2)
  215: 
  216: /* Interrupts */
  217: #define GT_INTRCAUSE            (0xc18 >> 2)
  218: #define GT_INTRMASK             (0xc1c >> 2)
  219: #define GT_PCI0_ICMASK          (0xc24 >> 2)
  220: #define GT_PCI0_SERR0MASK       (0xc28 >> 2)
  221: #define GT_CPU_INTSEL           (0xc70 >> 2)
  222: #define GT_PCI0_INTSEL          (0xc74 >> 2)
  223: #define GT_HINTRCAUSE           (0xc98 >> 2)
  224: #define GT_HINTRMASK            (0xc9c >> 2)
  225: #define GT_PCI0_HICMASK         (0xca4 >> 2)
  226: #define GT_PCI1_SERR1MASK       (0xca8 >> 2)
  227: 
  228: 
  229: typedef PCIHostState GT64120PCIState;
  230: 
  231: #define PCI_MAPPING_ENTRY(regname)            \
  232:     target_phys_addr_t regname ##_start;      \
  233:     target_phys_addr_t regname ##_length;     \
  234:     int regname ##_handle
  235: 
  236: typedef struct GT64120State {
  237:     GT64120PCIState *pci;
  238:     uint32_t regs[GT_REGS];
  239:     PCI_MAPPING_ENTRY(PCI0IO);
  240:     PCI_MAPPING_ENTRY(ISD);
  241: } GT64120State;
  242: 
  243: /* Adjust range to avoid touching space which isn't mappable via PCI */
  244: /* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
  245:                                     0x1fc00000 - 0x1fd00000  */
  246: static void check_reserved_space (target_phys_addr_t *start,
  247:                                   target_phys_addr_t *length)
  248: {
  249:     target_phys_addr_t begin = *start;
  250:     target_phys_addr_t end = *start + *length;
  251: 
  252:     if (end >= 0x1e000000LL && end < 0x1f100000LL)
  253:         end = 0x1e000000LL;
  254:     if (begin >= 0x1e000000LL && begin < 0x1f100000LL)
  255:         begin = 0x1f100000LL;
  256:     if (end >= 0x1fc00000LL && end < 0x1fd00000LL)
  257:         end = 0x1fc00000LL;
  258:     if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL)
  259:         begin = 0x1fd00000LL;
  260:     /* XXX: This is broken when a reserved range splits the requested range */
  261:     if (end >= 0x1f100000LL && begin < 0x1e000000LL)
  262:         end = 0x1e000000LL;
  263:     if (end >= 0x1fd00000LL && begin < 0x1fc00000LL)
  264:         end = 0x1fc00000LL;
  265: 
  266:     *start = begin;
  267:     *length = end - begin;
  268: }
  269: 
  270: static void gt64120_isd_mapping(GT64120State *s)
  271: {
  272:     target_phys_addr_t start = s->regs[GT_ISD] << 21;
  273:     target_phys_addr_t length = 0x1000;
  274: 
  275:     if (s->ISD_length)
  276:         cpu_register_physical_memory(s->ISD_start, s->ISD_length,
  277:                                      IO_MEM_UNASSIGNED);
  278:     check_reserved_space(&start, &length);
  279:     length = 0x1000;
  280:     /* Map new address */
  281:     dprintf("ISD: %x@%x -> %x@%x, %x\n", s->ISD_length, s->ISD_start,
  282:             length, start, s->ISD_handle);
  283:     s->ISD_start = start;
  284:     s->ISD_length = length;
  285:     cpu_register_physical_memory(s->ISD_start, s->ISD_length, s->ISD_handle);
  286: }
  287: 
  288: static void gt64120_pci_mapping(GT64120State *s)
  289: {
  290:     /* Update IO mapping */
  291:     if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
  292:     {
  293:       /* Unmap old IO address */
  294:       if (s->PCI0IO_length)
  295:       {
  296:         cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);
  297:       }
  298:       /* Map new IO address */
  299:       s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
  300:       s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
  301:       isa_mem_base = s->PCI0IO_start;
  302:       isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length);
  303:     }
  304: }
  305: 
  306: static void gt64120_writel (void *opaque, target_phys_addr_t addr,
  307:                             uint32_t val)
  308: {
  309:     GT64120State *s = opaque;
  310:     uint32_t saddr;
  311: 
  312:     if (!(s->regs[GT_PCI0_CMD] & 1))
  313:         val = bswap32(val);
  314: 
  315:     saddr = (addr & 0xfff) >> 2;
  316:     switch (saddr) {
  317: 
  318:     /* CPU Configuration */
  319:     case GT_CPU:
  320:         s->regs[GT_CPU] = val;
  321:         break;
  322:     case GT_MULTI:
  323:         /* Read-only register as only one GT64xxx is present on the CPU bus */
  324:         break;
  325: 
  326:     /* CPU Address Decode */
  327:     case GT_PCI0IOLD:
  328:         s->regs[GT_PCI0IOLD]    = val & 0x00007fff;
  329:         s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
  330:         gt64120_pci_mapping(s);
  331:         break;
  332:     case GT_PCI0M0LD:
  333:         s->regs[GT_PCI0M0LD]    = val & 0x00007fff;
  334:         s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
  335:         break;
  336:     case GT_PCI0M1LD:
  337:         s->regs[GT_PCI0M1LD]    = val & 0x00007fff;
  338:         s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
  339:         break;
  340:     case GT_PCI1IOLD:
  341:         s->regs[GT_PCI1IOLD]    = val & 0x00007fff;
  342:         s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
  343:         break;
  344:     case GT_PCI1M0LD:
  345:         s->regs[GT_PCI1M0LD]    = val & 0x00007fff;
  346:         s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
  347:         break;
  348:     case GT_PCI1M1LD:
  349:         s->regs[GT_PCI1M1LD]    = val & 0x00007fff;
  350:         s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
  351:         break;
  352:     case GT_PCI0IOHD:
  353:         s->regs[saddr] = val & 0x0000007f;
  354:         gt64120_pci_mapping(s);
  355:         break;
  356:     case GT_PCI0M0HD:
  357:     case GT_PCI0M1HD:
  358:     case GT_PCI1IOHD:
  359:     case GT_PCI1M0HD:
  360:     case GT_PCI1M1HD:
  361:         s->regs[saddr] = val & 0x0000007f;
  362:         break;
  363:     case GT_ISD:
  364:         s->regs[saddr] = val & 0x00007fff;
  365:         gt64120_isd_mapping(s);
  366:         break;
  367: 
  368:     case GT_PCI0IOREMAP:
  369:     case GT_PCI0M0REMAP:
  370:     case GT_PCI0M1REMAP:
  371:     case GT_PCI1IOREMAP:
  372:     case GT_PCI1M0REMAP:
  373:     case GT_PCI1M1REMAP:
  374:         s->regs[saddr] = val & 0x000007ff;
  375:         break;
  376: 
  377:     /* CPU Error Report */
  378:     case GT_CPUERR_ADDRLO:
  379:     case GT_CPUERR_ADDRHI:
  380:     case GT_CPUERR_DATALO:
  381:     case GT_CPUERR_DATAHI:
  382:     case GT_CPUERR_PARITY:
  383:         /* Read-only registers, do nothing */
  384:         break;
  385: 
  386:     /* CPU Sync Barrier */
  387:     case GT_PCI0SYNC:
  388:     case GT_PCI1SYNC:
  389:         /* Read-only registers, do nothing */
  390:         break;
  391: 
  392:     /* SDRAM and Device Address Decode */
  393:     case GT_SCS0LD:
  394:     case GT_SCS0HD:
  395:     case GT_SCS1LD:
  396:     case GT_SCS1HD:
  397:     case GT_SCS2LD:
  398:     case GT_SCS2HD:
  399:     case GT_SCS3LD:
  400:     case GT_SCS3HD:
  401:     case GT_CS0LD:
  402:     case GT_CS0HD:
  403:     case GT_CS1LD:
  404:     case GT_CS1HD:
  405:     case GT_CS2LD:
  406:     case GT_CS2HD:
  407:     case GT_CS3LD:
  408:     case GT_CS3HD:
  409:     case GT_BOOTLD:
  410:     case GT_BOOTHD:
  411:     case GT_ADERR:
  412:     /* SDRAM Configuration */
  413:     case GT_SDRAM_CFG:
  414:     case GT_SDRAM_OPMODE:
  415:     case GT_SDRAM_BM:
  416:     case GT_SDRAM_ADDRDECODE:
  417:         /* Accept and ignore SDRAM interleave configuration */
  418:         s->regs[saddr] = val;
  419:         break;
  420: 
  421:     /* Device Parameters */
  422:     case GT_DEV_B0:
  423:     case GT_DEV_B1:
  424:     case GT_DEV_B2:
  425:     case GT_DEV_B3:
  426:     case GT_DEV_BOOT:
  427:         /* Not implemented */
  428:         dprintf ("Unimplemented device register offset 0x%x\n", saddr << 2);
  429:         break;
  430: 
  431:     /* ECC */
  432:     case GT_ECC_ERRDATALO:
  433:     case GT_ECC_ERRDATAHI:
  434:     case GT_ECC_MEM:
  435:     case GT_ECC_CALC:
  436:     case GT_ECC_ERRADDR:
  437:         /* Read-only registers, do nothing */
  438:         break;
  439: 
  440:     /* DMA Record */
  441:     case GT_DMA0_CNT:
  442:     case GT_DMA1_CNT:
  443:     case GT_DMA2_CNT:
  444:     case GT_DMA3_CNT:
  445:     case GT_DMA0_SA:
  446:     case GT_DMA1_SA:
  447:     case GT_DMA2_SA:
  448:     case GT_DMA3_SA:
  449:     case GT_DMA0_DA:
  450:     case GT_DMA1_DA:
  451:     case GT_DMA2_DA:
  452:     case GT_DMA3_DA:
  453:     case GT_DMA0_NEXT:
  454:     case GT_DMA1_NEXT:
  455:     case GT_DMA2_NEXT:
  456:     case GT_DMA3_NEXT:
  457:     case GT_DMA0_CUR:
  458:     case GT_DMA1_CUR:
  459:     case GT_DMA2_CUR:
  460:     case GT_DMA3_CUR:
  461:         /* Not implemented */
  462:         dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
  463:         break;
  464: 
  465:     /* DMA Channel Control */
  466:     case GT_DMA0_CTRL:
  467:     case GT_DMA1_CTRL:
  468:     case GT_DMA2_CTRL:
  469:     case GT_DMA3_CTRL:
  470:         /* Not implemented */
  471:         dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
  472:         break;
  473: 
  474:     /* DMA Arbiter */
  475:     case GT_DMA_ARB:
  476:         /* Not implemented */
  477:         dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
  478:         break;
  479: 
  480:     /* Timer/Counter */
  481:     case GT_TC0:
  482:     case GT_TC1:
  483:     case GT_TC2:
  484:     case GT_TC3:
  485:     case GT_TC_CONTROL:
  486:         /* Not implemented */
  487:         dprintf ("Unimplemented timer register offset 0x%x\n", saddr << 2);
  488:         break;
  489: 
  490:     /* PCI Internal */
  491:     case GT_PCI0_CMD:
  492:     case GT_PCI1_CMD:
  493:         s->regs[saddr] = val & 0x0401fc0f;
  494:         break;
  495:     case GT_PCI0_TOR:
  496:     case GT_PCI0_BS_SCS10:
  497:     case GT_PCI0_BS_SCS32:
  498:     case GT_PCI0_BS_CS20:
  499:     case GT_PCI0_BS_CS3BT:
  500:     case GT_PCI1_IACK:
  501:     case GT_PCI0_IACK:
  502:     case GT_PCI0_BARE:
  503:     case GT_PCI0_PREFMBR: