1: 
    2: /* this struct defines the way the registers are stored on the
    3:    stack during a system call. */
    4: 
    5: struct target_pt_regs {
    6:     abi_long uregs[18];
    7: };
    8: 
    9: #define ARM_cpsr        uregs[16]
   10: #define ARM_pc          uregs[15]
   11: #define ARM_lr          uregs[14]
   12: #define ARM_sp          uregs[13]
   13: #define ARM_ip          uregs[12]
   14: #define ARM_fp          uregs[11]
   15: #define ARM_r10         uregs[10]
   16: #define ARM_r9          uregs[9]
   17: #define ARM_r8          uregs[8]
   18: #define ARM_r7          uregs[7]
   19: #define ARM_r6          uregs[6]
   20: #define ARM_r5          uregs[5]
   21: #define ARM_r4          uregs[4]
   22: #define ARM_r3          uregs[3]
   23: #define ARM_r2          uregs[2]
   24: #define ARM_r1          uregs[1]
   25: #define ARM_r0          uregs[0]
   26: #define ARM_ORIG_r0     uregs[17]
   27: 
   28: #define ARM_SYSCALL_BASE        0x900000
   29: #define ARM_THUMB_SYSCALL       0
   30: 
   31: #define ARM_NR_cacheflush (ARM_SYSCALL_BASE + 0xf0000 + 2)
   32: 
   33: #define ARM_NR_semihosting        0x123456
   34: #define ARM_NR_thumb_semihosting  0xAB
   35: 
   36: #if defined(TARGET_WORDS_BIGENDIAN)
   37: #define UNAME_MACHINE "armv5teb"
   38: #else
   39: #define UNAME_MACHINE "armv5tel"
   40: #endif
   41: 
   42: uint32_t do_arm_semihosting(CPUState *);