1: /* Print mips instructions for GDB, the GNU debugger, or for objdump. 2: Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3: 2000, 2001, 2002, 2003 4: Free Software Foundation, Inc. 5: Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp). 6: 7: This file is part of GDB, GAS, and the GNU binutils. 8: 9: This program is free software; you can redistribute it and/or modify 10: it under the terms of the GNU General Public License as published by 11: the Free Software Foundation; either version 2 of the License, or 12: (at your option) any later version. 13: 14: This program is distributed in the hope that it will be useful, 15: but WITHOUT ANY WARRANTY; without even the implied warranty of 16: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17: GNU General Public License for more details. 18: 19: You should have received a copy of the GNU General Public License 20: along with this program; if not, write to the Free Software 21: Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 22: 23: #include "dis-asm.h" 24: 25: /* mips.h. Mips opcode list for GDB, the GNU debugger. 26: Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 27: Free Software Foundation, Inc. 28: Contributed by Ralph Campbell and OSF 29: Commented and modified by Ian Lance Taylor, Cygnus Support 30: 31: This file is part of GDB, GAS, and the GNU binutils. 32: 33: GDB, GAS, and the GNU binutils are free software; you can redistribute 34: them and/or modify them under the terms of the GNU General Public 35: License as published by the Free Software Foundation; either version 36: 1, or (at your option) any later version. 37: 38: GDB, GAS, and the GNU binutils are distributed in the hope that they 39: will be useful, but WITHOUT ANY WARRANTY; without even the implied 40: warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 41: the GNU General Public License for more details. 42: 43: You should have received a copy of the GNU General Public License 44: along with this file; see the file COPYING. If not, write to the Free 45: Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 46: 47: /* mips.h. Mips opcode list for GDB, the GNU debugger. 48: Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 49: Free Software Foundation, Inc. 50: Contributed by Ralph Campbell and OSF 51: Commented and modified by Ian Lance Taylor, Cygnus Support 52: 53: This file is part of GDB, GAS, and the GNU binutils. 54: 55: GDB, GAS, and the GNU binutils are free software; you can redistribute 56: them and/or modify them under the terms of the GNU General Public 57: License as published by the Free Software Foundation; either version 58: 1, or (at your option) any later version. 59: 60: GDB, GAS, and the GNU binutils are distributed in the hope that they 61: will be useful, but WITHOUT ANY WARRANTY; without even the implied 62: warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 63: the GNU General Public License for more details. 64: 65: You should have received a copy of the GNU General Public License 66: along with this file; see the file COPYING. If not, write to the Free 67: Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 68: 69: /* These are bit masks and shift counts to use to access the various 70: fields of an instruction. To retrieve the X field of an 71: instruction, use the expression 72: (i >> OP_SH_X) & OP_MASK_X 73: To set the same field (to j), use 74: i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) 75: 76: Make sure you use fields that are appropriate for the instruction, 77: of course. 78: 79: The 'i' format uses OP, RS, RT and IMMEDIATE. 80: 81: The 'j' format uses OP and TARGET. 82: 83: The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. 84: 85: The 'b' format uses OP, RS, RT and DELTA. 86: 87: The floating point 'i' format uses OP, RS, RT and IMMEDIATE. 88: 89: The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. 90: 91: A breakpoint instruction uses OP, CODE and SPEC (10 bits of the 92: breakpoint instruction are not defined; Kane says the breakpoint 93: code field in BREAK is 20 bits; yet MIPS assemblers and debuggers 94: only use ten bits). An optional two-operand form of break/sdbbp 95: allows the lower ten bits to be set too, and MIPS32 and later 96: architectures allow 20 bits to be set with a signal operand 97: (using CODE20). 98: 99: The syscall instruction uses CODE20. 100: 101: The general coprocessor instructions use COPZ. */ 102: 103: #define OP_MASK_OP 0x3f 104: #define OP_SH_OP 26 105: #define OP_MASK_RS 0x1f 106: #define OP_SH_RS 21 107: #define OP_MASK_FR 0x1f 108: #define OP_SH_FR 21 109: #define OP_MASK_FMT 0x1f 110: #define OP_SH_FMT 21 111: #define OP_MASK_BCC 0x7 112: #define OP_SH_BCC 18 113: #define OP_MASK_CODE 0x3ff 114: #define OP_SH_CODE 16 115: #define OP_MASK_CODE2 0x3ff 116: #define OP_SH_CODE2 6 117: #define OP_MASK_RT 0x1f 118: #define OP_SH_RT 16 119: #define OP_MASK_FT 0x1f 120: #define OP_SH_FT 16 121: #define OP_MASK_CACHE 0x1f 122: #define OP_SH_CACHE 16 123: #define OP_MASK_RD 0x1f 124: #define OP_SH_RD 11 125: #define OP_MASK_FS 0x1f 126: #define OP_SH_FS 11 127: #define OP_MASK_PREFX 0x1f 128: #define OP_SH_PREFX 11 129: #define OP_MASK_CCC 0x7 130: #define OP_SH_CCC 8 131: #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ 132: #define OP_SH_CODE20 6 133: #define OP_MASK_SHAMT 0x1f 134: #define OP_SH_SHAMT 6 135: #define OP_MASK_FD 0x1f 136: #define OP_SH_FD 6 137: #define OP_MASK_TARGET 0x3ffffff 138: #define OP_SH_TARGET 0 139: #define OP_MASK_COPZ 0x1ffffff 140: #define OP_SH_COPZ 0 141: #define OP_MASK_IMMEDIATE 0xffff 142: #define OP_SH_IMMEDIATE 0 143: #define OP_MASK_DELTA 0xffff 144: #define OP_SH_DELTA 0 145: #define OP_MASK_FUNCT 0x3f 146: #define OP_SH_FUNCT 0 147: #define OP_MASK_SPEC 0x3f 148: #define OP_SH_SPEC 0 149: #define OP_SH_LOCC 8 /* FP condition code. */ 150: #define OP_SH_HICC 18 /* FP condition code. */ 151: #define OP_MASK_CC 0x7 152: #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ 153: #define OP_MASK_COP1NORM 0x1 /* a single bit. */ 154: #define OP_SH_COP1SPEC 21 /* COP1 encodings. */ 155: #define OP_MASK_COP1SPEC 0xf 156: #define OP_MASK_COP1SCLR 0x4 157: #define OP_MASK_COP1CMP 0x3 158: #define OP_SH_COP1CMP 4 159: #define OP_SH_FORMAT 21 /* FP short format field. */ 160: #define OP_MASK_FORMAT 0x7 161: #define OP_SH_TRUE 16 162: #define OP_MASK_TRUE 0x1 163: #define OP_SH_GE 17 164: #define OP_MASK_GE 0x01 165: #define OP_SH_UNSIGNED 16 166: #define OP_MASK_UNSIGNED 0x1 167: #define OP_SH_HINT 16 168: #define OP_MASK_HINT 0x1f 169: #define OP_SH_MMI 0 /* Multimedia (parallel) op. */ 170: #define OP_MASK_MMI 0x3f 171: #define OP_SH_MMISUB 6 172: #define OP_MASK_MMISUB 0x1f 173: #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ 174: #define OP_SH_PERFREG 1 175: #define OP_SH_SEL 0 /* Coprocessor select field. */ 176: #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ 177: #define OP_SH_CODE19 6 /* 19 bit wait code. */ 178: #define OP_MASK_CODE19 0x7ffff 179: #define OP_SH_ALN 21 180: #define OP_MASK_ALN 0x7 181: #define OP_SH_VSEL 21 182: #define OP_MASK_VSEL 0x1f 183: #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, 184: but 0x8-0xf don't select bytes. */ 185: #define OP_SH_VECBYTE 22 186: #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ 187: #define OP_SH_VECALIGN 21 188: #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ 189: #define OP_SH_INSMSB 11 190: #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ 191: #define OP_SH_EXTMSBD 11 192: 193: #define OP_OP_COP0 0x10 194: #define OP_OP_COP1 0x11 195: #define OP_OP_COP2 0x12 196: #define OP_OP_COP3 0x13 197: #define OP_OP_LWC1 0x31 198: #define OP_OP_LWC2 0x32 199: #define OP_OP_LWC3 0x33 /* a.k.a. pref */ 200: #define OP_OP_LDC1 0x35 201: #define OP_OP_LDC2 0x36 202: #define OP_OP_LDC3 0x37 /* a.k.a. ld */ 203: #define OP_OP_SWC1 0x39 204: #define OP_OP_SWC2 0x3a 205: #define OP_OP_SWC3 0x3b 206: #define OP_OP_SDC1 0x3d 207: #define OP_OP_SDC2 0x3e 208: #define OP_OP_SDC3 0x3f /* a.k.a. sd */ 209: 210: /* MIPS DSP ASE */ 211: #define OP_SH_DSPACC 11 212: #define OP_MASK_DSPACC 0x3 213: #define OP_SH_DSPACC_S 21 214: #define OP_MASK_DSPACC_S 0x3 215: #define OP_SH_DSPSFT 20 216: #define OP_MASK_DSPSFT 0x3f 217: #define OP_SH_DSPSFT_7 19 218: #define OP_MASK_DSPSFT_7 0x7f 219: #define OP_SH_SA3 21 220: #define OP_MASK_SA3 0x7 221: #define OP_SH_SA4 21 222: #define OP_MASK_SA4 0xf 223: #define OP_SH_IMM8 16 224: #define OP_MASK_IMM8 0xff 225: #define OP_SH_IMM10 16 226: #define OP_MASK_IMM10 0x3ff 227: #define OP_SH_WRDSP 11 228: #define OP_MASK_WRDSP 0x3f 229: #define OP_SH_RDDSP 16 230: #define OP_MASK_RDDSP 0x3f 231: #define OP_SH_BP 11 232: #define OP_MASK_BP 0x3 233: 234: /* MIPS MT ASE */ 235: #define OP_SH_MT_U 5 236: #define OP_MASK_MT_U 0x1 237: #define OP_SH_MT_H 4 238: #define OP_MASK_MT_H 0x1 239: #define OP_SH_MTACC_T 18 240: #define OP_MASK_MTACC_T 0x3 241: #define OP_SH_MTACC_D 13 242: #define OP_MASK_MTACC_D 0x3 243: 244: #define OP_OP_COP0 0x10 245: #define OP_OP_COP1 0x11 246: #define OP_OP_COP2 0x12 247: #define OP_OP_COP3 0x13 248: #define OP_OP_LWC1 0x31 249: #define OP_OP_LWC2 0x32 250: #define OP_OP_LWC3 0x33 /* a.k.a. pref */ 251: #define OP_OP_LDC1 0x35 252: #define OP_OP_LDC2 0x36 253: #define OP_OP_LDC3 0x37 /* a.k.a. ld */ 254: #define OP_OP_SWC1 0x39 255: #define OP_OP_SWC2 0x3a 256: #define OP_OP_SWC3 0x3b 257: #define OP_OP_SDC1 0x3d 258: #define OP_OP_SDC2 0x3e 259: #define OP_OP_SDC3 0x3f /* a.k.a. sd */ 260: 261: /* Values in the 'VSEL' field. */ 262: #define MDMX_FMTSEL_IMM_QH 0x1d 263: #define MDMX_FMTSEL_IMM_OB 0x1e 264: #define MDMX_FMTSEL_VEC_QH 0x15 265: #define MDMX_FMTSEL_VEC_OB 0x16 266: 267: /* UDI */ 268: #define OP_SH_UDI1 6 269: #define OP_MASK_UDI1 0x1f 270: #define OP_SH_UDI2 6 271: #define OP_MASK_UDI2 0x3ff 272: #define OP_SH_UDI3 6 273: #define OP_MASK_UDI3 0x7fff 274: #define OP_SH_UDI4 6 275: #define OP_MASK_UDI4 0xfffff 276: /* This structure holds information for a particular instruction. */ 277: 278: struct mips_opcode 279: { 280: /* The name of the instruction. */ 281: const char *name; 282: /* A string describing the arguments for this instruction. */ 283: const char *args; 284: /* The basic opcode for the instruction. When assembling, this 285: opcode is modified by the arguments to produce the actual opcode 286: that is used. If pinfo is INSN_MACRO, then this is 0. */ 287: unsigned long match; 288: /* If pinfo is not INSN_MACRO, then this is a bit mask for the 289: relevant portions of the opcode when disassembling. If the 290: actual opcode anded with the match field equals the opcode field, 291: then we have found the correct instruction. If pinfo is 292: INSN_MACRO, then this field is the macro identifier. */ 293: unsigned long mask; 294: /* For a macro, this is INSN_MACRO. Otherwise, it is a collection 295: of bits describing the instruction, notably any relevant hazard 296: information. */ 297: unsigned long pinfo; 298: /* A collection of additional bits describing the instruction. */ 299: unsigned long pinfo2; 300: /* A collection of bits describing the instruction sets of which this 301: instruction or macro is a member. */ 302: unsigned long membership; 303: }; 304: 305: /* These are the characters which may appear in the args field of an 306: instruction. They appear in the order in which the fields appear 307: when the instruction is used. Commas and parentheses in the args 308: string are ignored when assembling, and written into the output 309: when disassembling. 310: 311: Each of these characters corresponds to a mask field defined above. 312: 313: "<" 5 bit shift amount (OP_*_SHAMT) 314: ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) 315: "a" 26 bit target address (OP_*_TARGET) 316: "b" 5 bit base register (OP_*_RS) 317: "c" 10 bit breakpoint code (OP_*_CODE) 318: "d" 5 bit destination register specifier (OP_*_RD) 319: "h" 5 bit prefx hint (OP_*_PREFX) 320: "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) 321: "j" 16 bit signed immediate (OP_*_DELTA) 322: "k" 5 bit cache opcode in target register position (OP_*_CACHE) 323: Also used for immediate operands in vr5400 vector insns. 324: "o" 16 bit signed offset (OP_*_DELTA) 325: "p" 16 bit PC relative branch target address (OP_*_DELTA) 326: "q" 10 bit extra breakpoint code (OP_*_CODE2) 327: "r" 5 bit same register used as both source and target (OP_*_RS) 328: "s" 5 bit source register specifier (OP_*_RS) 329: "t" 5 bit target register (OP_*_RT) 330: "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) 331: "v" 5 bit same register used as both source and destination (OP_*_RS) 332: "w" 5 bit same register used as both target and destination (OP_*_RT) 333: "U" 5 bit same destination register in both OP_*_RD and OP_*_RT 334: (used by clo and clz) 335: "C" 25 bit coprocessor function code (OP_*_COPZ) 336: "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) 337: "J" 19 bit wait function code (OP_*_CODE19) 338: "x" accept and ignore register name 339: "z" must be zero register 340: "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) 341: "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes 342: LSB (OP_*_SHAMT). 343: Enforces: 0 <= pos < 32. 344: "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). 345: Requires that "+A" or "+E" occur first to set position. 346: Enforces: 0 < (pos+size) <= 32. 347: "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). 348: Requires that "+A" or "+E" occur first to set position. 349: Enforces: 0 < (pos+size) <= 32. 350: (Also used by "dext" w/ different limits, but limits for 351: that are checked by the M_DEXT macro.) 352: "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). 353: Enforces: 32 <= pos < 64. 354: "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). 355: Requires that "+A" or "+E" occur first to set position. 356: Enforces: 32 < (pos+size) <= 64. 357: "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). 358: Requires that "+A" or "+E" occur first to set position. 359: Enforces: 32 < (pos+size) <= 64. 360: "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). 361: Requires that "+A" or "+E" occur first to set position. 362: Enforces: 32 < (pos+size) <= 64. 363: 364: Floating point instructions: 365: "D" 5 bit destination register (OP_*_FD) 366: "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) 367: "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) 368: "S" 5 bit fs source 1 register (OP_*_FS) 369: "T" 5 bit ft source 2 register (OP_*_FT) 370: "R" 5 bit fr source 3 register (OP_*_FR) 371: "V" 5 bit same register used as floating source and destination (OP_*_FS) 372: "W" 5 bit same register used as floating target and destination (OP_*_FT) 373: 374: Coprocessor instructions: 375: "E" 5 bit target register (OP_*_RT) 376: "G" 5 bit destination register (OP_*_RD) 377: "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) 378: "P" 5 bit performance-monitor register (OP_*_PERFREG) 379: "e" 5 bit vector register byte specifier (OP_*_VECBYTE) 380: "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) 381: see also "k" above 382: "+D" Combined destination register ("G") and sel ("H") for CP0 ops, 383: for pretty-printing in disassembly only. 384: 385: Macro instructions: 386: "A" General 32 bit expression 387: "I" 32 bit immediate (value placed in imm_expr). 388: "+I" 32 bit immediate (value placed in imm2_expr). 389: "F" 64 bit floating point constant in .rdata 390: "L" 64 bit floating point constant in .lit8 391: "f" 32 bit floating point constant 392: "l" 32 bit floating point constant in .lit4 393: 394: MDMX instruction operands (note that while these use the FP register 395: fields, they accept both $fN and $vN names for the registers): 396: "O" MDMX alignment offset (OP_*_ALN) 397: "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) 398: "X" MDMX destination register (OP_*_FD) 399: "Y" MDMX source register (OP_*_FS) 400: "Z" MDMX source register (OP_*_FT) 401: 402: DSP ASE usage: 403: "2" 2 bit unsigned immediate for byte align (OP_*_BP) 404: "3" 3 bit unsigned immediate (OP_*_SA3) 405: "4" 4 bit unsigned immediate (OP_*_SA4) 406: "5" 8 bit unsigned immediate (OP_*_IMM8) 407: "6" 5 bit unsigned immediate (OP_*_RS) 408: "7" 2 bit dsp accumulator register (OP_*_DSPACC) 409: "8" 6 bit unsigned immediate (OP_*_WRDSP) 410: "9" 2 bit dsp accumulator register (OP_*_DSPACC_S) 411: "0" 6 bit signed immediate (OP_*_DSPSFT) 412: ":" 7 bit signed immediate (OP_*_DSPSFT_7) 413: "'" 6 bit unsigned immediate (OP_*_RDDSP) 414: "@" 10 bit signed immediate (OP_*_IMM10) 415: 416: MT ASE usage: 417: "!" 1 bit usermode flag (OP_*_MT_U) 418: "$" 1 bit load high flag (OP_*_MT_H) 419: "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) 420: "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) 421: "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) 422: "+t" 5 bit coprocessor 0 destination register (OP_*_RT) 423: "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only 424: 425: UDI immediates: 426: "+1" UDI immediate bits 6-10 427: "+2" UDI immediate bits 6-15 428: "+3" UDI immediate bits 6-20 429: "+4" UDI immediate bits 6-25 430: 431: Other: 432: "()" parens surrounding optional value 433: "," separates operands 434: "[]" brackets around index for vector-op scalar operand specifier (vr5400) 435: "+" Start of extension sequence. 436: 437: Characters used so far, for quick reference when adding more: 438: "234567890" 439: "%[]<>(),+:'@!$*&" 440: "ABCDEFGHIJKLMNOPQRSTUVWXYZ" 441: "abcdefghijklopqrstuvwxz" 442: 443: Extension character sequences used so far ("+" followed by the 444: following), for quick reference when adding more: 445: "1234" 446: "ABCDEFGHIT" 447: "t" 448: */ 449: 450: /* These are the bits which may be set in the pinfo field of an 451: instructions, if it is not equal to INSN_MACRO. */ 452: 453: /* Modifies the general purpose register in OP_*_RD. */ 454: #define INSN_WRITE_GPR_D 0x00000001 455: /* Modifies the general purpose register in OP_*_RT. */ 456: #define INSN_WRITE_GPR_T 0x00000002 457: /* Modifies general purpose register 31. */ 458: #define INSN_WRITE_GPR_31 0x00000004 459: /* Modifies the floating point register in OP_*_FD. */ 460: #define INSN_WRITE_FPR_D 0x00000008 461: /* Modifies the floating point register in OP_*_FS. */ 462: #define INSN_WRITE_FPR_S 0x00000010 463: /* Modifies the floating point register in OP_*_FT. */ 464: #define INSN_WRITE_FPR_T 0x00000020 465: /* Reads the general purpose register in OP_*_RS. */ 466: #define INSN_READ_GPR_S 0x00000040 467: /* Reads the general purpose register in OP_*_RT. */ 468: #define INSN_READ_GPR_T 0x00000080 469: /* Reads the floating point register in OP_*_FS. */ 470: #define INSN_READ_FPR_S 0x00000100 471: /* Reads the floating point register in OP_*_FT. */ 472: #define INSN_READ_FPR_T 0x00000200 473: /* Reads the floating point register in OP_*_FR. */ 474: #define INSN_READ_FPR_R 0x00000400 475: /* Modifies coprocessor condition code. */ 476: #define INSN_WRITE_COND_CODE 0x00000800 477: /* Reads coprocessor condition code. */ 478: #define INSN_READ_COND_CODE 0x00001000 479: /* TLB operation. */ 480: #define INSN_TLB 0x00002000 481: /* Reads coprocessor register other than floating point register. */ 482: #define INSN_COP 0x00004000 483: /* Instruction loads value from memory, requiring delay. */ 484: #define INSN_LOAD_MEMORY_DELAY 0x00008000 485: /* Instruction loads value from coprocessor, requiring delay. */ 486: #define INSN_LOAD_COPROC_DELAY 0x00010000 487: /* Instruction has unconditional branch delay slot. */ 488: #define INSN_UNCOND_BRANCH_DELAY 0x00020000 489: /* Instruction has conditional branch delay slot. */ 490: #define INSN_COND_BRANCH_DELAY 0x00040000 491: /* Conditional branch likely: if branch not taken, insn nullified. */ 492: #define INSN_COND_BRANCH_LIKELY 0x00080000 493: /* Moves to coprocessor register, requiring delay. */ 494: #define INSN_COPROC_MOVE_DELAY 0x00100000 495: /* Loads coprocessor register from memory, requiring delay. */ 496: #define INSN_COPROC_MEMORY_DELAY 0x00200000 497: /* Reads the HI register. */ 498: #define INSN_READ_HI 0x00400000 499: /* Reads the LO register. */ 500: #define INSN_READ_LO 0x00800000 501: /* Modifies the HI register. */ 502: #define INSN_WRITE_HI 0x01000000 503: /* Modifies the LO register. */ 504: #define INSN_WRITE_LO 0x02000000 505: /* Takes a trap (easier to keep out of delay slot). */ 506: #define INSN_TRAP 0x04000000 507: /* Instruction stores value into memory. */ 508: #define INSN_STORE_MEMORY 0x08000000 509: /* Instruction uses single precision floating point. */ 510: #define FP_S 0x10000000 511: /* Instruction uses double precision floating point. */ 512: #define FP_D 0x20000000 513: /* Instruction is part of the tx39's integer multiply family. */ 514: #define INSN_MULT 0x40000000 515: /* Instruction synchronize shared memory. */ 516: #define INSN_SYNC 0x80000000 517: 518: /* These are the bits which may be set in the pinfo2 field of an 519: instruction. */ 520: 521: /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ 522: #define INSN2_ALIAS 0x00000001 523: /* Instruction reads MDMX accumulator. */ 524: #define INSN2_READ_MDMX_ACC 0x00000002 525: /* Instruction writes MDMX accumulator. */ 526: #define INSN2_WRITE_MDMX_ACC 0x00000004 527: 528: /* Instruction is actually a macro. It should be ignored by the 529: disassembler, and requires special treatment by the assembler. */ 530: #define INSN_MACRO 0xffffffff 531: 532: